OLD | NEW |
1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
(...skipping 539 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
550 } T; | 550 } T; |
551 T t; | 551 T t; |
552 | 552 |
553 // Create a function that accepts &t, and loads, manipulates, and stores | 553 // Create a function that accepts &t, and loads, manipulates, and stores |
554 // the doubles t.a ... t.f. | 554 // the doubles t.a ... t.f. |
555 MacroAssembler assm(isolate, NULL, 0); | 555 MacroAssembler assm(isolate, NULL, 0); |
556 Label neither_is_nan, less_than, outa_here; | 556 Label neither_is_nan, less_than, outa_here; |
557 | 557 |
558 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) ); | 558 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) ); |
559 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) ); | 559 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) ); |
560 __ c(UN, D, f4, f6); | 560 if (kArchVariant != kMips64r6) { |
561 __ bc1f(&neither_is_nan); | 561 __ c(UN, D, f4, f6); |
| 562 __ bc1f(&neither_is_nan); |
| 563 } else { |
| 564 __ cmp(UN, L, f2, f4, f6); |
| 565 __ bc1eqz(&neither_is_nan, f2); |
| 566 } |
562 __ nop(); | 567 __ nop(); |
563 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) ); | 568 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) ); |
564 __ Branch(&outa_here); | 569 __ Branch(&outa_here); |
565 | 570 |
566 __ bind(&neither_is_nan); | 571 __ bind(&neither_is_nan); |
567 | 572 |
568 if (kArchVariant == kLoongson) { | 573 switch (kArchVariant) { |
569 __ c(OLT, D, f6, f4); | 574 case kLoongson: |
570 __ bc1t(&less_than); | 575 __ c(OLT, D, f6, f4); |
571 } else { | 576 __ bc1t(&less_than); |
572 __ c(OLT, D, f6, f4, 2); | 577 break; |
573 __ bc1t(&less_than, 2); | 578 case kMips64r6: |
| 579 __ cmp(OLT, L, f2, f6, f4); |
| 580 __ bc1nez(&less_than, f2); |
| 581 break; |
| 582 default: |
| 583 __ c(OLT, D, f6, f4, 2); |
| 584 __ bc1t(&less_than, 2); |
| 585 break; |
574 } | 586 } |
| 587 |
575 __ nop(); | 588 __ nop(); |
576 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) ); | 589 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) ); |
577 __ Branch(&outa_here); | 590 __ Branch(&outa_here); |
578 | 591 |
579 __ bind(&less_than); | 592 __ bind(&less_than); |
580 __ Addu(a4, zero_reg, Operand(1)); | 593 __ Addu(a4, zero_reg, Operand(1)); |
581 __ sw(a4, MemOperand(a0, OFFSET_OF(T, result)) ); // Set true. | 594 __ sw(a4, MemOperand(a0, OFFSET_OF(T, result)) ); // Set true. |
582 | 595 |
583 | 596 |
584 // This test-case should have additional tests. | 597 // This test-case should have additional tests. |
(...skipping 240 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
825 CHECK_EQ(2.147483647e9, t.a_converted); | 838 CHECK_EQ(2.147483647e9, t.a_converted); |
826 | 839 |
827 // 0xFF00FF00FF -> 1.095233372415e12. | 840 // 0xFF00FF00FF -> 1.095233372415e12. |
828 CHECK_EQ(1.095233372415e12, t.b); | 841 CHECK_EQ(1.095233372415e12, t.b); |
829 CHECK_EQ(0xFF00FF00FF, t.b_long_as_int64); | 842 CHECK_EQ(0xFF00FF00FF, t.b_long_as_int64); |
830 } | 843 } |
831 } | 844 } |
832 | 845 |
833 | 846 |
834 TEST(MIPS11) { | 847 TEST(MIPS11) { |
835 // Test LWL, LWR, SWL and SWR instructions. | 848 // Do not run test on MIPS64r6, as these instructions are removed. |
836 CcTest::InitializeVM(); | 849 if (kArchVariant != kMips64r6) { |
837 Isolate* isolate = CcTest::i_isolate(); | 850 // Test LWL, LWR, SWL and SWR instructions. |
838 HandleScope scope(isolate); | 851 CcTest::InitializeVM(); |
| 852 Isolate* isolate = CcTest::i_isolate(); |
| 853 HandleScope scope(isolate); |
839 | 854 |
840 typedef struct { | 855 typedef struct { |
841 int32_t reg_init; | 856 int32_t reg_init; |
842 int32_t mem_init; | 857 int32_t mem_init; |
843 int32_t lwl_0; | 858 int32_t lwl_0; |
844 int32_t lwl_1; | 859 int32_t lwl_1; |
845 int32_t lwl_2; | 860 int32_t lwl_2; |
846 int32_t lwl_3; | 861 int32_t lwl_3; |
847 int32_t lwr_0; | 862 int32_t lwr_0; |
848 int32_t lwr_1; | 863 int32_t lwr_1; |
849 int32_t lwr_2; | 864 int32_t lwr_2; |
850 int32_t lwr_3; | 865 int32_t lwr_3; |
851 int32_t swl_0; | 866 int32_t swl_0; |
852 int32_t swl_1; | 867 int32_t swl_1; |
853 int32_t swl_2; | 868 int32_t swl_2; |
854 int32_t swl_3; | 869 int32_t swl_3; |
855 int32_t swr_0; | 870 int32_t swr_0; |
856 int32_t swr_1; | 871 int32_t swr_1; |
857 int32_t swr_2; | 872 int32_t swr_2; |
858 int32_t swr_3; | 873 int32_t swr_3; |
859 } T; | 874 } T; |
860 T t; | 875 T t; |
861 | 876 |
862 Assembler assm(isolate, NULL, 0); | 877 Assembler assm(isolate, NULL, 0); |
863 | 878 |
864 // Test all combinations of LWL and vAddr. | 879 // Test all combinations of LWL and vAddr. |
865 __ lw(a4, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 880 __ lw(a4, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
866 __ lwl(a4, MemOperand(a0, OFFSET_OF(T, mem_init)) ); | 881 __ lwl(a4, MemOperand(a0, OFFSET_OF(T, mem_init)) ); |
867 __ sw(a4, MemOperand(a0, OFFSET_OF(T, lwl_0)) ); | 882 __ sw(a4, MemOperand(a0, OFFSET_OF(T, lwl_0)) ); |
868 | 883 |
869 __ lw(a5, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 884 __ lw(a5, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
870 __ lwl(a5, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) ); | 885 __ lwl(a5, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) ); |
871 __ sw(a5, MemOperand(a0, OFFSET_OF(T, lwl_1)) ); | 886 __ sw(a5, MemOperand(a0, OFFSET_OF(T, lwl_1)) ); |
872 | 887 |
873 __ lw(a6, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 888 __ lw(a6, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
874 __ lwl(a6, MemOperand(a0, OFFSET_OF(T, mem_init) + 2) ); | 889 __ lwl(a6, MemOperand(a0, OFFSET_OF(T, mem_init) + 2) ); |
875 __ sw(a6, MemOperand(a0, OFFSET_OF(T, lwl_2)) ); | 890 __ sw(a6, MemOperand(a0, OFFSET_OF(T, lwl_2)) ); |
876 | 891 |
877 __ lw(a7, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 892 __ lw(a7, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
878 __ lwl(a7, MemOperand(a0, OFFSET_OF(T, mem_init) + 3) ); | 893 __ lwl(a7, MemOperand(a0, OFFSET_OF(T, mem_init) + 3) ); |
879 __ sw(a7, MemOperand(a0, OFFSET_OF(T, lwl_3)) ); | 894 __ sw(a7, MemOperand(a0, OFFSET_OF(T, lwl_3)) ); |
880 | 895 |
881 // Test all combinations of LWR and vAddr. | 896 // Test all combinations of LWR and vAddr. |
882 __ lw(a4, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 897 __ lw(a4, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
883 __ lwr(a4, MemOperand(a0, OFFSET_OF(T, mem_init)) ); | 898 __ lwr(a4, MemOperand(a0, OFFSET_OF(T, mem_init)) ); |
884 __ sw(a4, MemOperand(a0, OFFSET_OF(T, lwr_0)) ); | 899 __ sw(a4, MemOperand(a0, OFFSET_OF(T, lwr_0)) ); |
885 | 900 |
886 __ lw(a5, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 901 __ lw(a5, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
887 __ lwr(a5, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) ); | 902 __ lwr(a5, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) ); |
888 __ sw(a5, MemOperand(a0, OFFSET_OF(T, lwr_1)) ); | 903 __ sw(a5, MemOperand(a0, OFFSET_OF(T, lwr_1)) ); |
889 | 904 |
890 __ lw(a6, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 905 __ lw(a6, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
891 __ lwr(a6, MemOperand(a0, OFFSET_OF(T, mem_init) + 2) ); | 906 __ lwr(a6, MemOperand(a0, OFFSET_OF(T, mem_init) + 2) ); |
892 __ sw(a6, MemOperand(a0, OFFSET_OF(T, lwr_2)) ); | 907 __ sw(a6, MemOperand(a0, OFFSET_OF(T, lwr_2)) ); |
893 | 908 |
894 __ lw(a7, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 909 __ lw(a7, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
895 __ lwr(a7, MemOperand(a0, OFFSET_OF(T, mem_init) + 3) ); | 910 __ lwr(a7, MemOperand(a0, OFFSET_OF(T, mem_init) + 3) ); |
896 __ sw(a7, MemOperand(a0, OFFSET_OF(T, lwr_3)) ); | 911 __ sw(a7, MemOperand(a0, OFFSET_OF(T, lwr_3)) ); |
897 | 912 |
898 // Test all combinations of SWL and vAddr. | 913 // Test all combinations of SWL and vAddr. |
899 __ lw(a4, MemOperand(a0, OFFSET_OF(T, mem_init)) ); | 914 __ lw(a4, MemOperand(a0, OFFSET_OF(T, mem_init)) ); |
900 __ sw(a4, MemOperand(a0, OFFSET_OF(T, swl_0)) ); | 915 __ sw(a4, MemOperand(a0, OFFSET_OF(T, swl_0)) ); |
901 __ lw(a4, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 916 __ lw(a4, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
902 __ swl(a4, MemOperand(a0, OFFSET_OF(T, swl_0)) ); | 917 __ swl(a4, MemOperand(a0, OFFSET_OF(T, swl_0)) ); |
903 | 918 |
904 __ lw(a5, MemOperand(a0, OFFSET_OF(T, mem_init)) ); | 919 __ lw(a5, MemOperand(a0, OFFSET_OF(T, mem_init)) ); |
905 __ sw(a5, MemOperand(a0, OFFSET_OF(T, swl_1)) ); | 920 __ sw(a5, MemOperand(a0, OFFSET_OF(T, swl_1)) ); |
906 __ lw(a5, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 921 __ lw(a5, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
907 __ swl(a5, MemOperand(a0, OFFSET_OF(T, swl_1) + 1) ); | 922 __ swl(a5, MemOperand(a0, OFFSET_OF(T, swl_1) + 1) ); |
908 | 923 |
909 __ lw(a6, MemOperand(a0, OFFSET_OF(T, mem_init)) ); | 924 __ lw(a6, MemOperand(a0, OFFSET_OF(T, mem_init)) ); |
910 __ sw(a6, MemOperand(a0, OFFSET_OF(T, swl_2)) ); | 925 __ sw(a6, MemOperand(a0, OFFSET_OF(T, swl_2)) ); |
911 __ lw(a6, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 926 __ lw(a6, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
912 __ swl(a6, MemOperand(a0, OFFSET_OF(T, swl_2) + 2) ); | 927 __ swl(a6, MemOperand(a0, OFFSET_OF(T, swl_2) + 2) ); |
913 | 928 |
914 __ lw(a7, MemOperand(a0, OFFSET_OF(T, mem_init)) ); | 929 __ lw(a7, MemOperand(a0, OFFSET_OF(T, mem_init)) ); |
915 __ sw(a7, MemOperand(a0, OFFSET_OF(T, swl_3)) ); | 930 __ sw(a7, MemOperand(a0, OFFSET_OF(T, swl_3)) ); |
916 __ lw(a7, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 931 __ lw(a7, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
917 __ swl(a7, MemOperand(a0, OFFSET_OF(T, swl_3) + 3) ); | 932 __ swl(a7, MemOperand(a0, OFFSET_OF(T, swl_3) + 3) ); |
918 | 933 |
919 // Test all combinations of SWR and vAddr. | 934 // Test all combinations of SWR and vAddr. |
920 __ lw(a4, MemOperand(a0, OFFSET_OF(T, mem_init)) ); | 935 __ lw(a4, MemOperand(a0, OFFSET_OF(T, mem_init)) ); |
921 __ sw(a4, MemOperand(a0, OFFSET_OF(T, swr_0)) ); | 936 __ sw(a4, MemOperand(a0, OFFSET_OF(T, swr_0)) ); |
922 __ lw(a4, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 937 __ lw(a4, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
923 __ swr(a4, MemOperand(a0, OFFSET_OF(T, swr_0)) ); | 938 __ swr(a4, MemOperand(a0, OFFSET_OF(T, swr_0)) ); |
924 | 939 |
925 __ lw(a5, MemOperand(a0, OFFSET_OF(T, mem_init)) ); | 940 __ lw(a5, MemOperand(a0, OFFSET_OF(T, mem_init)) ); |
926 __ sw(a5, MemOperand(a0, OFFSET_OF(T, swr_1)) ); | 941 __ sw(a5, MemOperand(a0, OFFSET_OF(T, swr_1)) ); |
927 __ lw(a5, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 942 __ lw(a5, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
928 __ swr(a5, MemOperand(a0, OFFSET_OF(T, swr_1) + 1) ); | 943 __ swr(a5, MemOperand(a0, OFFSET_OF(T, swr_1) + 1) ); |
929 | 944 |
930 __ lw(a6, MemOperand(a0, OFFSET_OF(T, mem_init)) ); | 945 __ lw(a6, MemOperand(a0, OFFSET_OF(T, mem_init)) ); |
931 __ sw(a6, MemOperand(a0, OFFSET_OF(T, swr_2)) ); | 946 __ sw(a6, MemOperand(a0, OFFSET_OF(T, swr_2)) ); |
932 __ lw(a6, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 947 __ lw(a6, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
933 __ swr(a6, MemOperand(a0, OFFSET_OF(T, swr_2) + 2) ); | 948 __ swr(a6, MemOperand(a0, OFFSET_OF(T, swr_2) + 2) ); |
934 | 949 |
935 __ lw(a7, MemOperand(a0, OFFSET_OF(T, mem_init)) ); | 950 __ lw(a7, MemOperand(a0, OFFSET_OF(T, mem_init)) ); |
936 __ sw(a7, MemOperand(a0, OFFSET_OF(T, swr_3)) ); | 951 __ sw(a7, MemOperand(a0, OFFSET_OF(T, swr_3)) ); |
937 __ lw(a7, MemOperand(a0, OFFSET_OF(T, reg_init)) ); | 952 __ lw(a7, MemOperand(a0, OFFSET_OF(T, reg_init)) ); |
938 __ swr(a7, MemOperand(a0, OFFSET_OF(T, swr_3) + 3) ); | 953 __ swr(a7, MemOperand(a0, OFFSET_OF(T, swr_3) + 3) ); |
939 | 954 |
940 __ jr(ra); | 955 __ jr(ra); |
941 __ nop(); | 956 __ nop(); |
942 | 957 |
943 CodeDesc desc; | 958 CodeDesc desc; |
944 assm.GetCode(&desc); | 959 assm.GetCode(&desc); |
945 Handle<Code> code = isolate->factory()->NewCode( | 960 Handle<Code> code = isolate->factory()->NewCode( |
946 desc, Code::ComputeFlags(Code::STUB), Handle<Code>()); | 961 desc, Code::ComputeFlags(Code::STUB), Handle<Code>()); |
947 F3 f = FUNCTION_CAST<F3>(code->entry()); | 962 F3 f = FUNCTION_CAST<F3>(code->entry()); |
948 t.reg_init = 0xaabbccdd; | 963 t.reg_init = 0xaabbccdd; |
949 t.mem_init = 0x11223344; | 964 t.mem_init = 0x11223344; |
950 | 965 |
951 Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0); | 966 Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0); |
952 USE(dummy); | 967 USE(dummy); |
953 | 968 |
954 CHECK_EQ(0x44bbccdd, t.lwl_0); | 969 CHECK_EQ(0x44bbccdd, t.lwl_0); |
955 CHECK_EQ(0x3344ccdd, t.lwl_1); | 970 CHECK_EQ(0x3344ccdd, t.lwl_1); |
956 CHECK_EQ(0x223344dd, t.lwl_2); | 971 CHECK_EQ(0x223344dd, t.lwl_2); |
957 CHECK_EQ(0x11223344, t.lwl_3); | 972 CHECK_EQ(0x11223344, t.lwl_3); |
958 | 973 |
959 CHECK_EQ(0x11223344, t.lwr_0); | 974 CHECK_EQ(0x11223344, t.lwr_0); |
960 CHECK_EQ(0xaa112233, t.lwr_1); | 975 CHECK_EQ(0xaa112233, t.lwr_1); |
961 CHECK_EQ(0xaabb1122, t.lwr_2); | 976 CHECK_EQ(0xaabb1122, t.lwr_2); |
962 CHECK_EQ(0xaabbcc11, t.lwr_3); | 977 CHECK_EQ(0xaabbcc11, t.lwr_3); |
963 | 978 |
964 CHECK_EQ(0x112233aa, t.swl_0); | 979 CHECK_EQ(0x112233aa, t.swl_0); |
965 CHECK_EQ(0x1122aabb, t.swl_1); | 980 CHECK_EQ(0x1122aabb, t.swl_1); |
966 CHECK_EQ(0x11aabbcc, t.swl_2); | 981 CHECK_EQ(0x11aabbcc, t.swl_2); |
967 CHECK_EQ(0xaabbccdd, t.swl_3); | 982 CHECK_EQ(0xaabbccdd, t.swl_3); |
968 | 983 |
969 CHECK_EQ(0xaabbccdd, t.swr_0); | 984 CHECK_EQ(0xaabbccdd, t.swr_0); |
970 CHECK_EQ(0xbbccdd44, t.swr_1); | 985 CHECK_EQ(0xbbccdd44, t.swr_1); |
971 CHECK_EQ(0xccdd3344, t.swr_2); | 986 CHECK_EQ(0xccdd3344, t.swr_2); |
972 CHECK_EQ(0xdd223344, t.swr_3); | 987 CHECK_EQ(0xdd223344, t.swr_3); |
| 988 } |
973 } | 989 } |
974 | 990 |
975 | 991 |
976 TEST(MIPS12) { | 992 TEST(MIPS12) { |
977 CcTest::InitializeVM(); | 993 CcTest::InitializeVM(); |
978 Isolate* isolate = CcTest::i_isolate(); | 994 Isolate* isolate = CcTest::i_isolate(); |
979 HandleScope scope(isolate); | 995 HandleScope scope(isolate); |
980 | 996 |
981 typedef struct { | 997 typedef struct { |
982 int32_t x; | 998 int32_t x; |
(...skipping 374 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1357 // Signed data, 32 & 64. | 1373 // Signed data, 32 & 64. |
1358 CHECK_EQ(0x33333333ffffbbccL, t.r3); | 1374 CHECK_EQ(0x33333333ffffbbccL, t.r3); |
1359 CHECK_EQ(0xffffffff0000bbccL, t.r4); | 1375 CHECK_EQ(0xffffffff0000bbccL, t.r4); |
1360 | 1376 |
1361 // Signed data, 32 & 64. | 1377 // Signed data, 32 & 64. |
1362 CHECK_EQ(0x55555555ffffffccL, t.r5); | 1378 CHECK_EQ(0x55555555ffffffccL, t.r5); |
1363 CHECK_EQ(0x000000003333bbccL, t.r6); | 1379 CHECK_EQ(0x000000003333bbccL, t.r6); |
1364 } | 1380 } |
1365 | 1381 |
1366 #undef __ | 1382 #undef __ |
OLD | NEW |