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Unified Diff: src/ia32/assembler-ia32.h

Issue 426233002: Land the Fan (disabled) (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Review feedback, rebase and "git cl format" Created 6 years, 5 months ago
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Index: src/ia32/assembler-ia32.h
diff --git a/src/ia32/assembler-ia32.h b/src/ia32/assembler-ia32.h
index de8b04f84e3e27287eaf0175d322545f1ce9cc3b..8b5f998f18c39caba8f5e85c222394976dcee083 100644
--- a/src/ia32/assembler-ia32.h
+++ b/src/ia32/assembler-ia32.h
@@ -300,6 +300,7 @@ class Immediate BASE_EMBEDDED {
int x_;
RelocInfo::Mode rmode_;
+ friend class Operand;
friend class Assembler;
friend class MacroAssembler;
};
@@ -322,12 +323,17 @@ enum ScaleFactor {
class Operand BASE_EMBEDDED {
public:
+ // reg
+ INLINE(explicit Operand(Register reg));
+
// XMM reg
INLINE(explicit Operand(XMMRegister xmm_reg));
// [disp/r]
INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
- // disp only must always be relocated
+
+ // [disp/r]
+ INLINE(explicit Operand(Immediate imm));
// [base + disp/r]
explicit Operand(Register base, int32_t disp,
@@ -364,6 +370,10 @@ class Operand BASE_EMBEDDED {
RelocInfo::CELL);
}
+ static Operand ForRegisterPlusImmediate(Register base, Immediate imm) {
+ return Operand(base, imm.x_, imm.rmode_);
+ }
+
// Returns true if this Operand is a wrapper for the specified register.
bool is_reg(Register reg) const;
@@ -375,9 +385,6 @@ class Operand BASE_EMBEDDED {
Register reg() const;
private:
- // reg
- INLINE(explicit Operand(Register reg));
-
// Set the ModRM byte without an encoded 'reg' register. The
// register is encoded later as part of the emit_operand operation.
inline void set_modrm(int mod, Register rm);
@@ -394,7 +401,6 @@ class Operand BASE_EMBEDDED {
friend class Assembler;
friend class MacroAssembler;
- friend class LCodeGen;
};
@@ -647,8 +653,9 @@ class Assembler : public AssemblerBase {
void rep_stos();
void stos();
- // Exchange two registers
+ // Exchange
void xchg(Register dst, Register src);
+ void xchg(Register dst, const Operand& src);
// Arithmetics
void adc(Register dst, int32_t imm32);
@@ -690,13 +697,17 @@ class Assembler : public AssemblerBase {
void cdq();
- void idiv(Register src);
+ void idiv(Register src) { idiv(Operand(src)); }
+ void idiv(const Operand& src);
+ void div(Register src) { div(Operand(src)); }
+ void div(const Operand& src);
// Signed multiply instructions.
void imul(Register src); // edx:eax = eax * src.
void imul(Register dst, Register src) { imul(dst, Operand(src)); }
void imul(Register dst, const Operand& src); // dst = dst * src.
void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
+ void imul(Register dst, const Operand& src, int32_t imm32);
void inc(Register dst);
void inc(const Operand& dst);
@@ -707,8 +718,10 @@ class Assembler : public AssemblerBase {
void mul(Register src); // edx:eax = eax * reg.
void neg(Register dst);
+ void neg(const Operand& dst);
void not_(Register dst);
+ void not_(const Operand& dst);
void or_(Register dst, int32_t imm32);
void or_(Register dst, Register src) { or_(dst, Operand(src)); }
@@ -722,22 +735,28 @@ class Assembler : public AssemblerBase {
void ror(Register dst, uint8_t imm8);
void ror_cl(Register dst);
- void sar(Register dst, uint8_t imm8);
- void sar_cl(Register dst);
+ void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
+ void sar(const Operand& dst, uint8_t imm8);
+ void sar_cl(Register dst) { sar_cl(Operand(dst)); }
+ void sar_cl(const Operand& dst);
void sbb(Register dst, const Operand& src);
void shld(Register dst, Register src) { shld(dst, Operand(src)); }
void shld(Register dst, const Operand& src);
- void shl(Register dst, uint8_t imm8);
- void shl_cl(Register dst);
+ void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); }
+ void shl(const Operand& dst, uint8_t imm8);
+ void shl_cl(Register dst) { shl_cl(Operand(dst)); }
+ void shl_cl(const Operand& dst);
void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
void shrd(Register dst, const Operand& src);
- void shr(Register dst, uint8_t imm8);
- void shr_cl(Register dst);
+ void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); }
+ void shr(const Operand& dst, uint8_t imm8);
+ void shr_cl(Register dst) { shr_cl(Operand(dst)); }
+ void shr_cl(const Operand& dst);
void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
void sub(const Operand& dst, const Immediate& x);
@@ -921,6 +940,9 @@ class Assembler : public AssemblerBase {
cvttss2si(dst, Operand(src));
}
void cvttsd2si(Register dst, const Operand& src);
+ void cvttsd2si(Register dst, XMMRegister src) {
+ cvttsd2si(dst, Operand(src));
+ }
void cvtsd2si(Register dst, XMMRegister src);
void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
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