| Index: src/arm/disasm-arm.cc
|
| diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
|
| index 70b1eb83b75fb7142c6553e0e4a8c654d6592259..604a2b88120d3d4591944dca153cbeea74f49e8b 100644
|
| --- a/src/arm/disasm-arm.cc
|
| +++ b/src/arm/disasm-arm.cc
|
| @@ -1097,13 +1097,16 @@ void Decoder::DecodeType3(Instruction* instr) {
|
| }
|
| case db_x: {
|
| if (FLAG_enable_sudiv) {
|
| - if (!instr->HasW()) {
|
| - if (instr->Bits(5, 4) == 0x1) {
|
| - if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) {
|
| + if (instr->Bits(5, 4) == 0x1) {
|
| + if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) {
|
| + if (instr->Bit(21) == 0x1) {
|
| + // UDIV (in V8 notation matching ARM ISA format) rn = rm/rs
|
| + Format(instr, "udiv'cond'b 'rn, 'rm, 'rs");
|
| + } else {
|
| // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs
|
| Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs");
|
| - break;
|
| }
|
| + break;
|
| }
|
| }
|
| }
|
|
|