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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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627 EnsureSpace ensure_space(this); | 627 EnsureSpace ensure_space(this); |
628 if (src.is(eax) || dst.is(eax)) { // Single-byte encoding. | 628 if (src.is(eax) || dst.is(eax)) { // Single-byte encoding. |
629 EMIT(0x90 | (src.is(eax) ? dst.code() : src.code())); | 629 EMIT(0x90 | (src.is(eax) ? dst.code() : src.code())); |
630 } else { | 630 } else { |
631 EMIT(0x87); | 631 EMIT(0x87); |
632 EMIT(0xC0 | src.code() << 3 | dst.code()); | 632 EMIT(0xC0 | src.code() << 3 | dst.code()); |
633 } | 633 } |
634 } | 634 } |
635 | 635 |
636 | 636 |
| 637 void Assembler::xchg(Register dst, const Operand& src) { |
| 638 EnsureSpace ensure_space(this); |
| 639 EMIT(0x87); |
| 640 emit_operand(dst, src); |
| 641 } |
| 642 |
| 643 |
637 void Assembler::adc(Register dst, int32_t imm32) { | 644 void Assembler::adc(Register dst, int32_t imm32) { |
638 EnsureSpace ensure_space(this); | 645 EnsureSpace ensure_space(this); |
639 emit_arith(2, Operand(dst), Immediate(imm32)); | 646 emit_arith(2, Operand(dst), Immediate(imm32)); |
640 } | 647 } |
641 | 648 |
642 | 649 |
643 void Assembler::adc(Register dst, const Operand& src) { | 650 void Assembler::adc(Register dst, const Operand& src) { |
644 EnsureSpace ensure_space(this); | 651 EnsureSpace ensure_space(this); |
645 EMIT(0x13); | 652 EMIT(0x13); |
646 emit_operand(dst, src); | 653 emit_operand(dst, src); |
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810 emit_operand(ecx, dst); | 817 emit_operand(ecx, dst); |
811 } | 818 } |
812 | 819 |
813 | 820 |
814 void Assembler::cdq() { | 821 void Assembler::cdq() { |
815 EnsureSpace ensure_space(this); | 822 EnsureSpace ensure_space(this); |
816 EMIT(0x99); | 823 EMIT(0x99); |
817 } | 824 } |
818 | 825 |
819 | 826 |
820 void Assembler::idiv(Register src) { | 827 void Assembler::idiv(const Operand& src) { |
821 EnsureSpace ensure_space(this); | 828 EnsureSpace ensure_space(this); |
822 EMIT(0xF7); | 829 EMIT(0xF7); |
823 EMIT(0xF8 | src.code()); | 830 emit_operand(edi, src); |
824 } | 831 } |
825 | 832 |
826 | 833 |
| 834 void Assembler::div(const Operand& src) { |
| 835 EnsureSpace ensure_space(this); |
| 836 EMIT(0xF7); |
| 837 emit_operand(esi, src); |
| 838 } |
| 839 |
| 840 |
827 void Assembler::imul(Register reg) { | 841 void Assembler::imul(Register reg) { |
828 EnsureSpace ensure_space(this); | 842 EnsureSpace ensure_space(this); |
829 EMIT(0xF7); | 843 EMIT(0xF7); |
830 EMIT(0xE8 | reg.code()); | 844 EMIT(0xE8 | reg.code()); |
831 } | 845 } |
832 | 846 |
833 | 847 |
834 void Assembler::imul(Register dst, const Operand& src) { | 848 void Assembler::imul(Register dst, const Operand& src) { |
835 EnsureSpace ensure_space(this); | 849 EnsureSpace ensure_space(this); |
836 EMIT(0x0F); | 850 EMIT(0x0F); |
837 EMIT(0xAF); | 851 EMIT(0xAF); |
838 emit_operand(dst, src); | 852 emit_operand(dst, src); |
839 } | 853 } |
840 | 854 |
841 | 855 |
842 void Assembler::imul(Register dst, Register src, int32_t imm32) { | 856 void Assembler::imul(Register dst, Register src, int32_t imm32) { |
| 857 imul(dst, Operand(src), imm32); |
| 858 } |
| 859 |
| 860 |
| 861 void Assembler::imul(Register dst, const Operand& src, int32_t imm32) { |
843 EnsureSpace ensure_space(this); | 862 EnsureSpace ensure_space(this); |
844 if (is_int8(imm32)) { | 863 if (is_int8(imm32)) { |
845 EMIT(0x6B); | 864 EMIT(0x6B); |
846 EMIT(0xC0 | dst.code() << 3 | src.code()); | 865 emit_operand(dst, src); |
847 EMIT(imm32); | 866 EMIT(imm32); |
848 } else { | 867 } else { |
849 EMIT(0x69); | 868 EMIT(0x69); |
850 EMIT(0xC0 | dst.code() << 3 | src.code()); | 869 emit_operand(dst, src); |
851 emit(imm32); | 870 emit(imm32); |
852 } | 871 } |
853 } | 872 } |
854 | 873 |
855 | 874 |
856 void Assembler::inc(Register dst) { | 875 void Assembler::inc(Register dst) { |
857 EnsureSpace ensure_space(this); | 876 EnsureSpace ensure_space(this); |
858 EMIT(0x40 | dst.code()); | 877 EMIT(0x40 | dst.code()); |
859 } | 878 } |
860 | 879 |
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880 } | 899 } |
881 | 900 |
882 | 901 |
883 void Assembler::neg(Register dst) { | 902 void Assembler::neg(Register dst) { |
884 EnsureSpace ensure_space(this); | 903 EnsureSpace ensure_space(this); |
885 EMIT(0xF7); | 904 EMIT(0xF7); |
886 EMIT(0xD8 | dst.code()); | 905 EMIT(0xD8 | dst.code()); |
887 } | 906 } |
888 | 907 |
889 | 908 |
| 909 void Assembler::neg(const Operand& dst) { |
| 910 EnsureSpace ensure_space(this); |
| 911 EMIT(0xF7); |
| 912 emit_operand(ebx, dst); |
| 913 } |
| 914 |
| 915 |
890 void Assembler::not_(Register dst) { | 916 void Assembler::not_(Register dst) { |
891 EnsureSpace ensure_space(this); | 917 EnsureSpace ensure_space(this); |
892 EMIT(0xF7); | 918 EMIT(0xF7); |
893 EMIT(0xD0 | dst.code()); | 919 EMIT(0xD0 | dst.code()); |
894 } | 920 } |
895 | 921 |
896 | 922 |
| 923 void Assembler::not_(const Operand& dst) { |
| 924 EnsureSpace ensure_space(this); |
| 925 EMIT(0xF7); |
| 926 emit_operand(edx, dst); |
| 927 } |
| 928 |
| 929 |
897 void Assembler::or_(Register dst, int32_t imm32) { | 930 void Assembler::or_(Register dst, int32_t imm32) { |
898 EnsureSpace ensure_space(this); | 931 EnsureSpace ensure_space(this); |
899 emit_arith(1, Operand(dst), Immediate(imm32)); | 932 emit_arith(1, Operand(dst), Immediate(imm32)); |
900 } | 933 } |
901 | 934 |
902 | 935 |
903 void Assembler::or_(Register dst, const Operand& src) { | 936 void Assembler::or_(Register dst, const Operand& src) { |
904 EnsureSpace ensure_space(this); | 937 EnsureSpace ensure_space(this); |
905 EMIT(0x0B); | 938 EMIT(0x0B); |
906 emit_operand(dst, src); | 939 emit_operand(dst, src); |
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962 } | 995 } |
963 | 996 |
964 | 997 |
965 void Assembler::ror_cl(Register dst) { | 998 void Assembler::ror_cl(Register dst) { |
966 EnsureSpace ensure_space(this); | 999 EnsureSpace ensure_space(this); |
967 EMIT(0xD3); | 1000 EMIT(0xD3); |
968 EMIT(0xC8 | dst.code()); | 1001 EMIT(0xC8 | dst.code()); |
969 } | 1002 } |
970 | 1003 |
971 | 1004 |
972 void Assembler::sar(Register dst, uint8_t imm8) { | 1005 void Assembler::sar(const Operand& dst, uint8_t imm8) { |
973 EnsureSpace ensure_space(this); | 1006 EnsureSpace ensure_space(this); |
974 ASSERT(is_uint5(imm8)); // illegal shift count | 1007 ASSERT(is_uint5(imm8)); // illegal shift count |
975 if (imm8 == 1) { | 1008 if (imm8 == 1) { |
976 EMIT(0xD1); | 1009 EMIT(0xD1); |
977 EMIT(0xF8 | dst.code()); | 1010 emit_operand(edi, dst); |
978 } else { | 1011 } else { |
979 EMIT(0xC1); | 1012 EMIT(0xC1); |
980 EMIT(0xF8 | dst.code()); | 1013 emit_operand(edi, dst); |
981 EMIT(imm8); | 1014 EMIT(imm8); |
982 } | 1015 } |
983 } | 1016 } |
984 | 1017 |
985 | 1018 |
986 void Assembler::sar_cl(Register dst) { | 1019 void Assembler::sar_cl(const Operand& dst) { |
987 EnsureSpace ensure_space(this); | 1020 EnsureSpace ensure_space(this); |
988 EMIT(0xD3); | 1021 EMIT(0xD3); |
989 EMIT(0xF8 | dst.code()); | 1022 emit_operand(edi, dst); |
990 } | 1023 } |
991 | 1024 |
992 | 1025 |
993 void Assembler::sbb(Register dst, const Operand& src) { | 1026 void Assembler::sbb(Register dst, const Operand& src) { |
994 EnsureSpace ensure_space(this); | 1027 EnsureSpace ensure_space(this); |
995 EMIT(0x1B); | 1028 EMIT(0x1B); |
996 emit_operand(dst, src); | 1029 emit_operand(dst, src); |
997 } | 1030 } |
998 | 1031 |
999 | 1032 |
1000 void Assembler::shld(Register dst, const Operand& src) { | 1033 void Assembler::shld(Register dst, const Operand& src) { |
1001 EnsureSpace ensure_space(this); | 1034 EnsureSpace ensure_space(this); |
1002 EMIT(0x0F); | 1035 EMIT(0x0F); |
1003 EMIT(0xA5); | 1036 EMIT(0xA5); |
1004 emit_operand(dst, src); | 1037 emit_operand(dst, src); |
1005 } | 1038 } |
1006 | 1039 |
1007 | 1040 |
1008 void Assembler::shl(Register dst, uint8_t imm8) { | 1041 void Assembler::shl(const Operand& dst, uint8_t imm8) { |
1009 EnsureSpace ensure_space(this); | 1042 EnsureSpace ensure_space(this); |
1010 ASSERT(is_uint5(imm8)); // illegal shift count | 1043 ASSERT(is_uint5(imm8)); // illegal shift count |
1011 if (imm8 == 1) { | 1044 if (imm8 == 1) { |
1012 EMIT(0xD1); | 1045 EMIT(0xD1); |
1013 EMIT(0xE0 | dst.code()); | 1046 emit_operand(esp, dst); |
1014 } else { | 1047 } else { |
1015 EMIT(0xC1); | 1048 EMIT(0xC1); |
1016 EMIT(0xE0 | dst.code()); | 1049 emit_operand(esp, dst); |
1017 EMIT(imm8); | 1050 EMIT(imm8); |
1018 } | 1051 } |
1019 } | 1052 } |
1020 | 1053 |
1021 | 1054 |
1022 void Assembler::shl_cl(Register dst) { | 1055 void Assembler::shl_cl(const Operand& dst) { |
1023 EnsureSpace ensure_space(this); | 1056 EnsureSpace ensure_space(this); |
1024 EMIT(0xD3); | 1057 EMIT(0xD3); |
1025 EMIT(0xE0 | dst.code()); | 1058 emit_operand(esp, dst); |
1026 } | 1059 } |
1027 | 1060 |
1028 | 1061 |
1029 void Assembler::shrd(Register dst, const Operand& src) { | 1062 void Assembler::shrd(Register dst, const Operand& src) { |
1030 EnsureSpace ensure_space(this); | 1063 EnsureSpace ensure_space(this); |
1031 EMIT(0x0F); | 1064 EMIT(0x0F); |
1032 EMIT(0xAD); | 1065 EMIT(0xAD); |
1033 emit_operand(dst, src); | 1066 emit_operand(dst, src); |
1034 } | 1067 } |
1035 | 1068 |
1036 | 1069 |
1037 void Assembler::shr(Register dst, uint8_t imm8) { | 1070 void Assembler::shr(const Operand& dst, uint8_t imm8) { |
1038 EnsureSpace ensure_space(this); | 1071 EnsureSpace ensure_space(this); |
1039 ASSERT(is_uint5(imm8)); // illegal shift count | 1072 ASSERT(is_uint5(imm8)); // illegal shift count |
1040 if (imm8 == 1) { | 1073 if (imm8 == 1) { |
1041 EMIT(0xD1); | 1074 EMIT(0xD1); |
1042 EMIT(0xE8 | dst.code()); | 1075 emit_operand(ebp, dst); |
1043 } else { | 1076 } else { |
1044 EMIT(0xC1); | 1077 EMIT(0xC1); |
1045 EMIT(0xE8 | dst.code()); | 1078 emit_operand(ebp, dst); |
1046 EMIT(imm8); | 1079 EMIT(imm8); |
1047 } | 1080 } |
1048 } | 1081 } |
1049 | 1082 |
1050 | 1083 |
1051 void Assembler::shr_cl(Register dst) { | 1084 void Assembler::shr_cl(const Operand& dst) { |
1052 EnsureSpace ensure_space(this); | 1085 EnsureSpace ensure_space(this); |
1053 EMIT(0xD3); | 1086 EMIT(0xD3); |
1054 EMIT(0xE8 | dst.code()); | 1087 emit_operand(ebp, dst); |
1055 } | 1088 } |
1056 | 1089 |
1057 | 1090 |
1058 void Assembler::sub(const Operand& dst, const Immediate& x) { | 1091 void Assembler::sub(const Operand& dst, const Immediate& x) { |
1059 EnsureSpace ensure_space(this); | 1092 EnsureSpace ensure_space(this); |
1060 emit_arith(5, dst, x); | 1093 emit_arith(5, dst, x); |
1061 } | 1094 } |
1062 | 1095 |
1063 | 1096 |
1064 void Assembler::sub(Register dst, const Operand& src) { | 1097 void Assembler::sub(Register dst, const Operand& src) { |
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2637 fprintf(coverage_log, "%s\n", file_line); | 2670 fprintf(coverage_log, "%s\n", file_line); |
2638 fflush(coverage_log); | 2671 fflush(coverage_log); |
2639 } | 2672 } |
2640 } | 2673 } |
2641 | 2674 |
2642 #endif | 2675 #endif |
2643 | 2676 |
2644 } } // namespace v8::internal | 2677 } } // namespace v8::internal |
2645 | 2678 |
2646 #endif // V8_TARGET_ARCH_IA32 | 2679 #endif // V8_TARGET_ARCH_IA32 |
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