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Issue 426233002: Land the Fan (disabled) (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Review feedback, rebase and "git cl format" Created 6 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #ifndef V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
6 #define V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
7
8 namespace v8 {
9 namespace internal {
10 namespace compiler {
11
12 // X64-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V) \
15 V(X64Add) \
16 V(X64Add32) \
17 V(X64And) \
18 V(X64And32) \
19 V(X64Cmp) \
20 V(X64Cmp32) \
21 V(X64Test) \
22 V(X64Test32) \
23 V(X64Or) \
24 V(X64Or32) \
25 V(X64Xor) \
26 V(X64Xor32) \
27 V(X64Sub) \
28 V(X64Sub32) \
29 V(X64Imul) \
30 V(X64Imul32) \
31 V(X64Idiv) \
32 V(X64Idiv32) \
33 V(X64Udiv) \
34 V(X64Udiv32) \
35 V(X64Not) \
36 V(X64Not32) \
37 V(X64Neg) \
38 V(X64Neg32) \
39 V(X64Shl) \
40 V(X64Shl32) \
41 V(X64Shr) \
42 V(X64Shr32) \
43 V(X64Sar) \
44 V(X64Sar32) \
45 V(X64Push) \
46 V(X64PushI) \
47 V(X64CallCodeObject) \
48 V(X64CallAddress) \
49 V(PopStack) \
50 V(X64CallJSFunction) \
51 V(SSEFloat64Cmp) \
52 V(SSEFloat64Add) \
53 V(SSEFloat64Sub) \
54 V(SSEFloat64Mul) \
55 V(SSEFloat64Div) \
56 V(SSEFloat64Mod) \
57 V(X64Int32ToInt64) \
58 V(X64Int64ToInt32) \
59 V(SSEFloat64ToInt32) \
60 V(SSEInt32ToFloat64) \
61 V(SSELoad) \
62 V(SSEStore) \
63 V(X64LoadWord8) \
64 V(X64StoreWord8) \
65 V(X64StoreWord8I) \
66 V(X64LoadWord16) \
67 V(X64StoreWord16) \
68 V(X64StoreWord16I) \
69 V(X64LoadWord32) \
70 V(X64StoreWord32) \
71 V(X64StoreWord32I) \
72 V(X64LoadWord64) \
73 V(X64StoreWord64) \
74 V(X64StoreWord64I) \
75 V(X64StoreWriteBarrier)
76
77
78 // Addressing modes represent the "shape" of inputs to an instruction.
79 // Many instructions support multiple addressing modes. Addressing modes
80 // are encoded into the InstructionCode of the instruction and tell the
81 // code generator after register allocation which assembler method to call.
82 //
83 // We use the following local notation for addressing modes:
84 //
85 // R = register
86 // O = register or stack slot
87 // D = double register
88 // I = immediate (handle, external, int32)
89 // MR = [register]
90 // MI = [immediate]
91 // MRN = [register + register * N in {1, 2, 4, 8}]
92 // MRI = [register + immediate]
93 // MRNI = [register + register * N in {1, 2, 4, 8} + immediate]
94 #define TARGET_ADDRESSING_MODE_LIST(V) \
95 V(MR) /* [%r1] */ \
96 V(MRI) /* [%r1 + K] */ \
97 V(MR1I) /* [%r1 + %r2 + K] */ \
98 V(MR2I) /* [%r1 + %r2*2 + K] */ \
99 V(MR4I) /* [%r1 + %r2*4 + K] */ \
100 V(MR8I) /* [%r1 + %r2*8 + K] */
101
102 } // namespace compiler
103 } // namespace internal
104 } // namespace v8
105
106 #endif // V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
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