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Side by Side Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 426233002: Land the Fan (disabled) (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Review feedback, rebase and "git cl format" Created 6 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
7
8 namespace v8 {
9 namespace internal {
10 namespace compiler {
11
12 // ARM64-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V) \
15 V(Arm64Add) \
16 V(Arm64Add32) \
17 V(Arm64And) \
18 V(Arm64And32) \
19 V(Arm64Cmp) \
20 V(Arm64Cmp32) \
21 V(Arm64Tst) \
22 V(Arm64Tst32) \
23 V(Arm64Or) \
24 V(Arm64Or32) \
25 V(Arm64Xor) \
26 V(Arm64Xor32) \
27 V(Arm64Sub) \
28 V(Arm64Sub32) \
29 V(Arm64Mul) \
30 V(Arm64Mul32) \
31 V(Arm64Idiv) \
32 V(Arm64Idiv32) \
33 V(Arm64Udiv) \
34 V(Arm64Udiv32) \
35 V(Arm64Imod) \
36 V(Arm64Imod32) \
37 V(Arm64Umod) \
38 V(Arm64Umod32) \
39 V(Arm64Not) \
40 V(Arm64Not32) \
41 V(Arm64Neg) \
42 V(Arm64Neg32) \
43 V(Arm64Shl) \
44 V(Arm64Shl32) \
45 V(Arm64Shr) \
46 V(Arm64Shr32) \
47 V(Arm64Sar) \
48 V(Arm64Sar32) \
49 V(Arm64CallCodeObject) \
50 V(Arm64CallJSFunction) \
51 V(Arm64CallAddress) \
52 V(Arm64Claim) \
53 V(Arm64Poke) \
54 V(Arm64PokePairZero) \
55 V(Arm64PokePair) \
56 V(Arm64Drop) \
57 V(Arm64Float64Cmp) \
58 V(Arm64Float64Add) \
59 V(Arm64Float64Sub) \
60 V(Arm64Float64Mul) \
61 V(Arm64Float64Div) \
62 V(Arm64Float64Mod) \
63 V(Arm64Int32ToInt64) \
64 V(Arm64Int64ToInt32) \
65 V(Arm64Float64ToInt32) \
66 V(Arm64Int32ToFloat64) \
67 V(Arm64Float64Load) \
68 V(Arm64Float64Store) \
69 V(Arm64LoadWord8) \
70 V(Arm64StoreWord8) \
71 V(Arm64LoadWord16) \
72 V(Arm64StoreWord16) \
73 V(Arm64LoadWord32) \
74 V(Arm64StoreWord32) \
75 V(Arm64LoadWord64) \
76 V(Arm64StoreWord64) \
77 V(Arm64StoreWriteBarrier)
78
79
80 // Addressing modes represent the "shape" of inputs to an instruction.
81 // Many instructions support multiple addressing modes. Addressing modes
82 // are encoded into the InstructionCode of the instruction and tell the
83 // code generator after register allocation which assembler method to call.
84 //
85 // We use the following local notation for addressing modes:
86 //
87 // R = register
88 // O = register or stack slot
89 // D = double register
90 // I = immediate (handle, external, int32)
91 // MRI = [register + immediate]
92 // MRR = [register + register]
93 #define TARGET_ADDRESSING_MODE_LIST(V) \
94 V(MRI) /* [%r0 + K] */ \
95 V(MRR) /* [%r0 + %r1] */
96
97 } // namespace internal
98 } // namespace compiler
99 } // namespace v8
100
101 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
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