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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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1090 UNREACHABLE(); | 1090 UNREACHABLE(); |
1091 } | 1091 } |
1092 break; | 1092 break; |
1093 } | 1093 } |
1094 } | 1094 } |
1095 } | 1095 } |
1096 break; | 1096 break; |
1097 } | 1097 } |
1098 case db_x: { | 1098 case db_x: { |
1099 if (FLAG_enable_sudiv) { | 1099 if (FLAG_enable_sudiv) { |
1100 if (!instr->HasW()) { | 1100 if (instr->Bits(5, 4) == 0x1) { |
1101 if (instr->Bits(5, 4) == 0x1) { | 1101 if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) { |
1102 if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) { | 1102 if (instr->Bit(21) == 0x1) { |
| 1103 // UDIV (in V8 notation matching ARM ISA format) rn = rm/rs |
| 1104 Format(instr, "udiv'cond'b 'rn, 'rm, 'rs"); |
| 1105 } else { |
1103 // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs | 1106 // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs |
1104 Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs"); | 1107 Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs"); |
1105 break; | |
1106 } | 1108 } |
| 1109 break; |
1107 } | 1110 } |
1108 } | 1111 } |
1109 } | 1112 } |
1110 Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w"); | 1113 Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w"); |
1111 break; | 1114 break; |
1112 } | 1115 } |
1113 case ib_x: { | 1116 case ib_x: { |
1114 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) { | 1117 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) { |
1115 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16)); | 1118 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16)); |
1116 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7)); | 1119 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7)); |
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1778 v8::internal::PrintF( | 1781 v8::internal::PrintF( |
1779 f, "%p %08x %s\n", | 1782 f, "%p %08x %s\n", |
1780 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1783 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1781 } | 1784 } |
1782 } | 1785 } |
1783 | 1786 |
1784 | 1787 |
1785 } // namespace disasm | 1788 } // namespace disasm |
1786 | 1789 |
1787 #endif // V8_TARGET_ARCH_ARM | 1790 #endif // V8_TARGET_ARCH_ARM |
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