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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1537 | 1537 |
1538 void Assembler::sdiv(Register dst, Register src1, Register src2, | 1538 void Assembler::sdiv(Register dst, Register src1, Register src2, |
1539 Condition cond) { | 1539 Condition cond) { |
1540 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); | 1540 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
1541 ASSERT(IsEnabled(SUDIV)); | 1541 ASSERT(IsEnabled(SUDIV)); |
1542 emit(cond | B26 | B25| B24 | B20 | dst.code()*B16 | 0xf * B12 | | 1542 emit(cond | B26 | B25| B24 | B20 | dst.code()*B16 | 0xf * B12 | |
1543 src2.code()*B8 | B4 | src1.code()); | 1543 src2.code()*B8 | B4 | src1.code()); |
1544 } | 1544 } |
1545 | 1545 |
1546 | 1546 |
| 1547 void Assembler::udiv(Register dst, Register src1, Register src2, |
| 1548 Condition cond) { |
| 1549 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
| 1550 ASSERT(IsEnabled(SUDIV)); |
| 1551 emit(cond | B26 | B25 | B24 | B21 | B20 | dst.code() * B16 | 0xf * B12 | |
| 1552 src2.code() * B8 | B4 | src1.code()); |
| 1553 } |
| 1554 |
| 1555 |
1547 void Assembler::mul(Register dst, Register src1, Register src2, | 1556 void Assembler::mul(Register dst, Register src1, Register src2, |
1548 SBit s, Condition cond) { | 1557 SBit s, Condition cond) { |
1549 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); | 1558 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
1550 // dst goes in bits 16-19 for this instruction! | 1559 // dst goes in bits 16-19 for this instruction! |
1551 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); | 1560 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); |
1552 } | 1561 } |
1553 | 1562 |
1554 | 1563 |
1555 void Assembler::smlal(Register dstL, | 1564 void Assembler::smlal(Register dstL, |
1556 Register dstH, | 1565 Register dstH, |
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2149 sub(ip, base, Operand(offset)); | 2158 sub(ip, base, Operand(offset)); |
2150 } | 2159 } |
2151 emit(cond | 0xD*B24 | d*B22 | B20 | ip.code()*B16 | vd*B12 | 0xB*B8); | 2160 emit(cond | 0xD*B24 | d*B22 | B20 | ip.code()*B16 | vd*B12 | 0xB*B8); |
2152 } | 2161 } |
2153 } | 2162 } |
2154 | 2163 |
2155 | 2164 |
2156 void Assembler::vldr(const DwVfpRegister dst, | 2165 void Assembler::vldr(const DwVfpRegister dst, |
2157 const MemOperand& operand, | 2166 const MemOperand& operand, |
2158 const Condition cond) { | 2167 const Condition cond) { |
2159 ASSERT(!operand.rm().is_valid()); | |
2160 ASSERT(operand.am_ == Offset); | 2168 ASSERT(operand.am_ == Offset); |
2161 vldr(dst, operand.rn(), operand.offset(), cond); | 2169 if (operand.rm().is_valid()) { |
| 2170 add(ip, operand.rn(), |
| 2171 Operand(operand.rm(), operand.shift_op_, operand.shift_imm_)); |
| 2172 vldr(dst, ip, 0, cond); |
| 2173 } else { |
| 2174 vldr(dst, operand.rn(), operand.offset(), cond); |
| 2175 } |
2162 } | 2176 } |
2163 | 2177 |
2164 | 2178 |
2165 void Assembler::vldr(const SwVfpRegister dst, | 2179 void Assembler::vldr(const SwVfpRegister dst, |
2166 const Register base, | 2180 const Register base, |
2167 int offset, | 2181 int offset, |
2168 const Condition cond) { | 2182 const Condition cond) { |
2169 // Sdst = MEM(Rbase + offset). | 2183 // Sdst = MEM(Rbase + offset). |
2170 // Instruction details available in ARM DDI 0406A, A8-628. | 2184 // Instruction details available in ARM DDI 0406A, A8-628. |
2171 // cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) | | 2185 // cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) | |
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2192 sub(ip, base, Operand(offset)); | 2206 sub(ip, base, Operand(offset)); |
2193 } | 2207 } |
2194 emit(cond | d*B22 | 0xD1*B20 | ip.code()*B16 | sd*B12 | 0xA*B8); | 2208 emit(cond | d*B22 | 0xD1*B20 | ip.code()*B16 | sd*B12 | 0xA*B8); |
2195 } | 2209 } |
2196 } | 2210 } |
2197 | 2211 |
2198 | 2212 |
2199 void Assembler::vldr(const SwVfpRegister dst, | 2213 void Assembler::vldr(const SwVfpRegister dst, |
2200 const MemOperand& operand, | 2214 const MemOperand& operand, |
2201 const Condition cond) { | 2215 const Condition cond) { |
2202 ASSERT(!operand.rm().is_valid()); | |
2203 ASSERT(operand.am_ == Offset); | 2216 ASSERT(operand.am_ == Offset); |
2204 vldr(dst, operand.rn(), operand.offset(), cond); | 2217 if (operand.rm().is_valid()) { |
| 2218 add(ip, operand.rn(), |
| 2219 Operand(operand.rm(), operand.shift_op_, operand.shift_imm_)); |
| 2220 vldr(dst, ip, 0, cond); |
| 2221 } else { |
| 2222 vldr(dst, operand.rn(), operand.offset(), cond); |
| 2223 } |
2205 } | 2224 } |
2206 | 2225 |
2207 | 2226 |
2208 void Assembler::vstr(const DwVfpRegister src, | 2227 void Assembler::vstr(const DwVfpRegister src, |
2209 const Register base, | 2228 const Register base, |
2210 int offset, | 2229 int offset, |
2211 const Condition cond) { | 2230 const Condition cond) { |
2212 // MEM(Rbase + offset) = Dsrc. | 2231 // MEM(Rbase + offset) = Dsrc. |
2213 // Instruction details available in ARM DDI 0406C.b, A8-1082. | 2232 // Instruction details available in ARM DDI 0406C.b, A8-1082. |
2214 // cond(31-28) | 1101(27-24)| U(23) | D(22) | 00(21-20) | Rbase(19-16) | | 2233 // cond(31-28) | 1101(27-24)| U(23) | D(22) | 00(21-20) | Rbase(19-16) | |
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2235 sub(ip, base, Operand(offset)); | 2254 sub(ip, base, Operand(offset)); |
2236 } | 2255 } |
2237 emit(cond | 0xD*B24 | d*B22 | ip.code()*B16 | vd*B12 | 0xB*B8); | 2256 emit(cond | 0xD*B24 | d*B22 | ip.code()*B16 | vd*B12 | 0xB*B8); |
2238 } | 2257 } |
2239 } | 2258 } |
2240 | 2259 |
2241 | 2260 |
2242 void Assembler::vstr(const DwVfpRegister src, | 2261 void Assembler::vstr(const DwVfpRegister src, |
2243 const MemOperand& operand, | 2262 const MemOperand& operand, |
2244 const Condition cond) { | 2263 const Condition cond) { |
2245 ASSERT(!operand.rm().is_valid()); | |
2246 ASSERT(operand.am_ == Offset); | 2264 ASSERT(operand.am_ == Offset); |
2247 vstr(src, operand.rn(), operand.offset(), cond); | 2265 if (operand.rm().is_valid()) { |
| 2266 add(ip, operand.rn(), |
| 2267 Operand(operand.rm(), operand.shift_op_, operand.shift_imm_)); |
| 2268 vstr(src, ip, 0, cond); |
| 2269 } else { |
| 2270 vstr(src, operand.rn(), operand.offset(), cond); |
| 2271 } |
2248 } | 2272 } |
2249 | 2273 |
2250 | 2274 |
2251 void Assembler::vstr(const SwVfpRegister src, | 2275 void Assembler::vstr(const SwVfpRegister src, |
2252 const Register base, | 2276 const Register base, |
2253 int offset, | 2277 int offset, |
2254 const Condition cond) { | 2278 const Condition cond) { |
2255 // MEM(Rbase + offset) = SSrc. | 2279 // MEM(Rbase + offset) = SSrc. |
2256 // Instruction details available in ARM DDI 0406A, A8-786. | 2280 // Instruction details available in ARM DDI 0406A, A8-786. |
2257 // cond(31-28) | 1101(27-24)| U000(23-20) | Rbase(19-16) | | 2281 // cond(31-28) | 1101(27-24)| U000(23-20) | Rbase(19-16) | |
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2277 sub(ip, base, Operand(offset)); | 2301 sub(ip, base, Operand(offset)); |
2278 } | 2302 } |
2279 emit(cond | d*B22 | 0xD0*B20 | ip.code()*B16 | sd*B12 | 0xA*B8); | 2303 emit(cond | d*B22 | 0xD0*B20 | ip.code()*B16 | sd*B12 | 0xA*B8); |
2280 } | 2304 } |
2281 } | 2305 } |
2282 | 2306 |
2283 | 2307 |
2284 void Assembler::vstr(const SwVfpRegister src, | 2308 void Assembler::vstr(const SwVfpRegister src, |
2285 const MemOperand& operand, | 2309 const MemOperand& operand, |
2286 const Condition cond) { | 2310 const Condition cond) { |
2287 ASSERT(!operand.rm().is_valid()); | |
2288 ASSERT(operand.am_ == Offset); | 2311 ASSERT(operand.am_ == Offset); |
2289 vstr(src, operand.rn(), operand.offset(), cond); | 2312 if (operand.rm().is_valid()) { |
| 2313 add(ip, operand.rn(), |
| 2314 Operand(operand.rm(), operand.shift_op_, operand.shift_imm_)); |
| 2315 vstr(src, ip, 0, cond); |
| 2316 } else { |
| 2317 vstr(src, operand.rn(), operand.offset(), cond); |
| 2318 } |
2290 } | 2319 } |
2291 | 2320 |
2292 | 2321 |
2293 void Assembler::vldm(BlockAddrMode am, | 2322 void Assembler::vldm(BlockAddrMode am, |
2294 Register base, | 2323 Register base, |
2295 DwVfpRegister first, | 2324 DwVfpRegister first, |
2296 DwVfpRegister last, | 2325 DwVfpRegister last, |
2297 Condition cond) { | 2326 Condition cond) { |
2298 // Instruction details available in ARM DDI 0406C.b, A8-922. | 2327 // Instruction details available in ARM DDI 0406C.b, A8-922. |
2299 // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) | | 2328 // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) | |
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3118 } | 3147 } |
3119 | 3148 |
3120 | 3149 |
3121 bool Assembler::IsNop(Instr instr, int type) { | 3150 bool Assembler::IsNop(Instr instr, int type) { |
3122 ASSERT(0 <= type && type <= 14); // mov pc, pc isn't a nop. | 3151 ASSERT(0 <= type && type <= 14); // mov pc, pc isn't a nop. |
3123 // Check for mov rx, rx where x = type. | 3152 // Check for mov rx, rx where x = type. |
3124 return instr == (al | 13*B21 | type*B12 | type); | 3153 return instr == (al | 13*B21 | type*B12 | type); |
3125 } | 3154 } |
3126 | 3155 |
3127 | 3156 |
| 3157 // static |
3128 bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) { | 3158 bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) { |
3129 uint32_t dummy1; | 3159 uint32_t dummy1; |
3130 uint32_t dummy2; | 3160 uint32_t dummy2; |
3131 return fits_shifter(imm32, &dummy1, &dummy2, NULL); | 3161 return fits_shifter(imm32, &dummy1, &dummy2, NULL); |
3132 } | 3162 } |
3133 | 3163 |
3134 | 3164 |
3135 bool Assembler::ImmediateFitsAddrMode2Instruction(int32_t imm32) { | 3165 bool Assembler::ImmediateFitsAddrMode2Instruction(int32_t imm32) { |
3136 return is_uint12(abs(imm32)); | 3166 return is_uint12(abs(imm32)); |
3137 } | 3167 } |
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3733 assm->instr_at_put( | 3763 assm->instr_at_put( |
3734 rinfo.pc(), Assembler::SetLdrRegisterImmediateOffset(instr, offset)); | 3764 rinfo.pc(), Assembler::SetLdrRegisterImmediateOffset(instr, offset)); |
3735 } | 3765 } |
3736 } | 3766 } |
3737 } | 3767 } |
3738 | 3768 |
3739 | 3769 |
3740 } } // namespace v8::internal | 3770 } } // namespace v8::internal |
3741 | 3771 |
3742 #endif // V8_TARGET_ARCH_ARM | 3772 #endif // V8_TARGET_ARCH_ARM |
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