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Issue 422063005: Contribution of PowerPC port. (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: re-upload - catch up to 8/19 level Created 6 years, 3 months ago
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« Makefile ('K') | « src/base/build_config.h ('k') | src/base/cpu.cc » ('j') | src/base/platform/platform-posix.cc » ('J')
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1 // Copyright 2006-2013 the V8 project authors. All rights reserved. 1 // Copyright 2006-2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // This module contains the architecture-specific code. This make the rest of 5 // This module contains the architecture-specific code. This make the rest of
6 // the code less dependent on differences between different processor 6 // the code less dependent on differences between different processor
7 // architecture. 7 // architecture.
8 // The classes have the same definition for all architectures. The 8 // The classes have the same definition for all architectures. The
9 // implementation for a particular architecture is put in cpu_<arch>.cc. 9 // implementation for a particular architecture is put in cpu_<arch>.cc.
10 // The build system then uses the implementation for the target architecture. 10 // The build system then uses the implementation for the target architecture.
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
48 static const int QUALCOMM = 0x51; 48 static const int QUALCOMM = 0x51;
49 int architecture() const { return architecture_; } 49 int architecture() const { return architecture_; }
50 int part() const { return part_; } 50 int part() const { return part_; }
51 static const int ARM_CORTEX_A5 = 0xc05; 51 static const int ARM_CORTEX_A5 = 0xc05;
52 static const int ARM_CORTEX_A7 = 0xc07; 52 static const int ARM_CORTEX_A7 = 0xc07;
53 static const int ARM_CORTEX_A8 = 0xc08; 53 static const int ARM_CORTEX_A8 = 0xc08;
54 static const int ARM_CORTEX_A9 = 0xc09; 54 static const int ARM_CORTEX_A9 = 0xc09;
55 static const int ARM_CORTEX_A12 = 0xc0c; 55 static const int ARM_CORTEX_A12 = 0xc0c;
56 static const int ARM_CORTEX_A15 = 0xc0f; 56 static const int ARM_CORTEX_A15 = 0xc0f;
57 57
58 // PPC-specific part codes
59 int cache_line_size() const { return cache_line_size_; }
60 enum {
61 PPC_POWER5,
62 PPC_POWER6,
63 PPC_POWER7,
64 PPC_POWER8,
65 PPC_G4,
66 PPC_G5,
67 PPC_PA6T
68 };
69
58 // General features 70 // General features
59 bool has_fpu() const { return has_fpu_; } 71 bool has_fpu() const { return has_fpu_; }
60 72
61 // x86 features 73 // x86 features
62 bool has_cmov() const { return has_cmov_; } 74 bool has_cmov() const { return has_cmov_; }
63 bool has_sahf() const { return has_sahf_; } 75 bool has_sahf() const { return has_sahf_; }
64 bool has_mmx() const { return has_mmx_; } 76 bool has_mmx() const { return has_mmx_; }
65 bool has_sse() const { return has_sse_; } 77 bool has_sse() const { return has_sse_; }
66 bool has_sse2() const { return has_sse2_; } 78 bool has_sse2() const { return has_sse2_; }
67 bool has_sse3() const { return has_sse3_; } 79 bool has_sse3() const { return has_sse3_; }
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84 char vendor_[13]; 96 char vendor_[13];
85 int stepping_; 97 int stepping_;
86 int model_; 98 int model_;
87 int ext_model_; 99 int ext_model_;
88 int family_; 100 int family_;
89 int ext_family_; 101 int ext_family_;
90 int type_; 102 int type_;
91 int implementer_; 103 int implementer_;
92 int architecture_; 104 int architecture_;
93 int part_; 105 int part_;
106 int cache_line_size_;
94 bool has_fpu_; 107 bool has_fpu_;
95 bool has_cmov_; 108 bool has_cmov_;
96 bool has_sahf_; 109 bool has_sahf_;
97 bool has_mmx_; 110 bool has_mmx_;
98 bool has_sse_; 111 bool has_sse_;
99 bool has_sse2_; 112 bool has_sse2_;
100 bool has_sse3_; 113 bool has_sse3_;
101 bool has_ssse3_; 114 bool has_ssse3_;
102 bool has_sse41_; 115 bool has_sse41_;
103 bool has_sse42_; 116 bool has_sse42_;
104 bool has_idiva_; 117 bool has_idiva_;
105 bool has_neon_; 118 bool has_neon_;
106 bool has_thumb2_; 119 bool has_thumb2_;
107 bool has_vfp_; 120 bool has_vfp_;
108 bool has_vfp3_; 121 bool has_vfp3_;
109 bool has_vfp3_d32_; 122 bool has_vfp3_d32_;
110 bool is_fp64_mode_; 123 bool is_fp64_mode_;
111 }; 124 };
112 125
113 } } // namespace v8::base 126 } } // namespace v8::base
114 127
115 #endif // V8_BASE_CPU_H_ 128 #endif // V8_BASE_CPU_H_
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