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Side by Side Diff: src/IceTargetLoweringX8632.cpp

Issue 417353003: Fix bug when atomic load is fused with an arith op (and not in the entry BB) (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: review Created 6 years, 4 months ago
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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the TargetLoweringX8632 class, which 10 // This file implements the TargetLoweringX8632 class, which
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2717 // normally does (split the load into two). 2717 // normally does (split the load into two).
2718 // Thus, this skips load/arithmetic op folding. Load/arithmetic folding 2718 // Thus, this skips load/arithmetic op folding. Load/arithmetic folding
2719 // can't happen anyway, since this is x86-32 and integer arithmetic only 2719 // can't happen anyway, since this is x86-32 and integer arithmetic only
2720 // happens on 32-bit quantities. 2720 // happens on 32-bit quantities.
2721 Variable *T = makeReg(IceType_f64); 2721 Variable *T = makeReg(IceType_f64);
2722 OperandX8632Mem *Addr = FormMemoryOperand(Instr->getArg(0), IceType_f64); 2722 OperandX8632Mem *Addr = FormMemoryOperand(Instr->getArg(0), IceType_f64);
2723 _movq(T, Addr); 2723 _movq(T, Addr);
2724 // Then cast the bits back out of the XMM register to the i64 Dest. 2724 // Then cast the bits back out of the XMM register to the i64 Dest.
2725 InstCast *Cast = InstCast::create(Func, InstCast::Bitcast, Dest, T); 2725 InstCast *Cast = InstCast::create(Func, InstCast::Bitcast, Dest, T);
2726 lowerCast(Cast); 2726 lowerCast(Cast);
2727 // Make sure that the atomic load isn't elided. 2727 // Make sure that the atomic load isn't elided when unused.
2728 Context.insert(InstFakeUse::create(Func, Dest->getLo())); 2728 Context.insert(InstFakeUse::create(Func, Dest->getLo()));
2729 Context.insert(InstFakeUse::create(Func, Dest->getHi())); 2729 Context.insert(InstFakeUse::create(Func, Dest->getHi()));
2730 return; 2730 return;
2731 } 2731 }
2732 InstLoad *Load = InstLoad::create(Func, Dest, Instr->getArg(0)); 2732 InstLoad *Load = InstLoad::create(Func, Dest, Instr->getArg(0));
2733 lowerLoad(Load); 2733 lowerLoad(Load);
2734 // Make sure the atomic load isn't elided. 2734 // Make sure the atomic load isn't elided when unused, by adding a FakeUse.
2735 Context.insert(InstFakeUse::create(Func, Dest)); 2735 // Since lowerLoad may fuse the load w/ an arithmetic instruction,
2736 // insert the FakeUse on the last-inserted instruction's dest.
2737 Context.insert(InstFakeUse::create(Func,
2738 Context.getLastInserted()->getDest()));
2736 return; 2739 return;
2737 } 2740 }
2738 case Intrinsics::AtomicRMW: 2741 case Intrinsics::AtomicRMW:
2739 if (!Intrinsics::VerifyMemoryOrder( 2742 if (!Intrinsics::VerifyMemoryOrder(
2740 llvm::cast<ConstantInteger>(Instr->getArg(3))->getValue())) { 2743 llvm::cast<ConstantInteger>(Instr->getArg(3))->getValue())) {
2741 Func->setError("Unexpected memory ordering for AtomicRMW"); 2744 Func->setError("Unexpected memory ordering for AtomicRMW");
2742 return; 2745 return;
2743 } 2746 }
2744 lowerAtomicRMW(Instr->getDest(), 2747 lowerAtomicRMW(Instr->getDest(),
2745 static_cast<uint32_t>(llvm::cast<ConstantInteger>( 2748 static_cast<uint32_t>(llvm::cast<ConstantInteger>(
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4087 for (SizeT i = 0; i < Size; ++i) { 4090 for (SizeT i = 0; i < Size; ++i) {
4088 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n"; 4091 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n";
4089 } 4092 }
4090 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; 4093 Str << "\t.size\t" << MangledName << ", " << Size << "\n";
4091 } 4094 }
4092 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName 4095 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName
4093 << "\n"; 4096 << "\n";
4094 } 4097 }
4095 4098
4096 } // end of namespace Ice 4099 } // end of namespace Ice
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