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Side by Side Diff: src/IceTargetLoweringX8632.cpp

Issue 417353003: Fix bug when atomic load is fused with an arith op (and not in the entry BB) (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: or do getLast by rewinding from Next Created 6 years, 4 months ago
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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the TargetLoweringX8632 class, which 10 // This file implements the TargetLoweringX8632 class, which
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2720 // normally does (split the load into two). 2720 // normally does (split the load into two).
2721 // Thus, this skips load/arithmetic op folding. Load/arithmetic folding 2721 // Thus, this skips load/arithmetic op folding. Load/arithmetic folding
2722 // can't happen anyway, since this is x86-32 and integer arithmetic only 2722 // can't happen anyway, since this is x86-32 and integer arithmetic only
2723 // happens on 32-bit quantities. 2723 // happens on 32-bit quantities.
2724 Variable *T = makeReg(IceType_f64); 2724 Variable *T = makeReg(IceType_f64);
2725 OperandX8632Mem *Addr = FormMemoryOperand(Instr->getArg(0), IceType_f64); 2725 OperandX8632Mem *Addr = FormMemoryOperand(Instr->getArg(0), IceType_f64);
2726 _movq(T, Addr); 2726 _movq(T, Addr);
2727 // Then cast the bits back out of the XMM register to the i64 Dest. 2727 // Then cast the bits back out of the XMM register to the i64 Dest.
2728 InstCast *Cast = InstCast::create(Func, InstCast::Bitcast, Dest, T); 2728 InstCast *Cast = InstCast::create(Func, InstCast::Bitcast, Dest, T);
2729 lowerCast(Cast); 2729 lowerCast(Cast);
2730 // Make sure that the atomic load isn't elided. 2730 // Make sure that the atomic load isn't elided when unused.
2731 Context.insert(InstFakeUse::create(Func, Dest->getLo())); 2731 Context.insert(InstFakeUse::create(Func, Dest->getLo()));
2732 Context.insert(InstFakeUse::create(Func, Dest->getHi())); 2732 Context.insert(InstFakeUse::create(Func, Dest->getHi()));
2733 return; 2733 return;
2734 } 2734 }
2735 InstLoad *Load = InstLoad::create(Func, Dest, Instr->getArg(0)); 2735 InstLoad *Load = InstLoad::create(Func, Dest, Instr->getArg(0));
2736 lowerLoad(Load); 2736 lowerLoad(Load);
2737 // Make sure the atomic load isn't elided. 2737 // Make sure the atomic load isn't elided when unused, by adding a FakeUse.
2738 Context.insert(InstFakeUse::create(Func, Dest)); 2738 // Since lowerLoad may fuse the load w/ an arithmetic instruction,
2739 // insert the FakeUse on the last-inserted instruction's dest.
2740 Context.insert(InstFakeUse::create(Func,
2741 Context.getLastInserted()->getDest()));
2739 return; 2742 return;
2740 } 2743 }
2741 case Intrinsics::AtomicRMW: 2744 case Intrinsics::AtomicRMW:
2742 if (!Intrinsics::VerifyMemoryOrder( 2745 if (!Intrinsics::VerifyMemoryOrder(
2743 llvm::cast<ConstantInteger>(Instr->getArg(3))->getValue())) { 2746 llvm::cast<ConstantInteger>(Instr->getArg(3))->getValue())) {
2744 Func->setError("Unexpected memory ordering for AtomicRMW"); 2747 Func->setError("Unexpected memory ordering for AtomicRMW");
2745 return; 2748 return;
2746 } 2749 }
2747 lowerAtomicRMW(Instr->getDest(), 2750 lowerAtomicRMW(Instr->getDest(),
2748 static_cast<uint32_t>(llvm::cast<ConstantInteger>( 2751 static_cast<uint32_t>(llvm::cast<ConstantInteger>(
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4017 for (SizeT i = 0; i < Size; ++i) { 4020 for (SizeT i = 0; i < Size; ++i) {
4018 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n"; 4021 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n";
4019 } 4022 }
4020 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; 4023 Str << "\t.size\t" << MangledName << ", " << Size << "\n";
4021 } 4024 }
4022 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName 4025 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName
4023 << "\n"; 4026 << "\n";
4024 } 4027 }
4025 4028
4026 } // end of namespace Ice 4029 } // end of namespace Ice
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