OLD | NEW |
1 ; This tests each of the supported NaCl atomic instructions for every | 1 ; This tests each of the supported NaCl atomic instructions for every |
2 ; size allowed. | 2 ; size allowed. |
3 | 3 |
4 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s | 4 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s |
5 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s --check-prefix=CHECKO2REM | 5 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s --check-prefix=CHECKO2 |
6 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s | 6 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s |
7 ; RUN: %llvm2ice -O2 --verbose none %s \ | 7 ; RUN: %llvm2ice -O2 --verbose none %s \ |
8 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj | 8 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj |
9 ; RUN: %llvm2ice -Om1 --verbose none %s \ | 9 ; RUN: %llvm2ice -Om1 --verbose none %s \ |
10 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj | 10 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj |
11 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s | 11 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s |
12 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s | 12 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s |
13 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ | 13 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ |
14 ; RUN: | FileCheck --check-prefix=DUMP %s | 14 ; RUN: | FileCheck --check-prefix=DUMP %s |
15 | 15 |
(...skipping 792 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
808 ret i64 0 | 808 ret i64 0 |
809 } | 809 } |
810 ; CHECK-LABEL: test_atomic_cmpxchg_64_ignored | 810 ; CHECK-LABEL: test_atomic_cmpxchg_64_ignored |
811 ; CHECK: push ebx | 811 ; CHECK: push ebx |
812 ; CHECK-DAG: mov edx | 812 ; CHECK-DAG: mov edx |
813 ; CHECK-DAG: mov eax | 813 ; CHECK-DAG: mov eax |
814 ; CHECK-DAG: mov ecx | 814 ; CHECK-DAG: mov ecx |
815 ; CHECK-DAG: mov ebx | 815 ; CHECK-DAG: mov ebx |
816 ; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}] | 816 ; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}] |
817 | 817 |
818 define i32 @test_atomic_cmpxchg_32_loop(i32 %iptr, i32 %expected, i32 %desired)
{ | |
819 entry: | |
820 br label %loop | |
821 | |
822 loop: | |
823 %cmp = phi i32 [ %expected, %entry ], [ %old, %loop ] | |
824 %ptr = inttoptr i32 %iptr to i32* | |
825 %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %cmp, | |
826 i32 %desired, i32 6, i32 6) | |
827 %success = icmp eq i32 %cmp, %old | |
828 br i1 %success, label %done, label %loop | |
829 | |
830 done: | |
831 ret i32 %old | |
832 } | |
833 ; CHECK-LABEL: test_atomic_cmpxchg_32_loop | |
834 | |
835 ;;;; Fence and is-lock-free. | 818 ;;;; Fence and is-lock-free. |
836 | 819 |
837 define void @test_atomic_fence() { | 820 define void @test_atomic_fence() { |
838 entry: | 821 entry: |
839 call void @llvm.nacl.atomic.fence(i32 6) | 822 call void @llvm.nacl.atomic.fence(i32 6) |
840 ret void | 823 ret void |
841 } | 824 } |
842 ; CHECK-LABEL: test_atomic_fence | 825 ; CHECK-LABEL: test_atomic_fence |
843 ; CHECK: mfence | 826 ; CHECK: mfence |
844 | 827 |
(...skipping 27 matching lines...) Expand all Loading... |
872 | 855 |
873 define i32 @test_atomic_is_lock_free_ignored(i32 %iptr) { | 856 define i32 @test_atomic_is_lock_free_ignored(i32 %iptr) { |
874 entry: | 857 entry: |
875 %ptr = inttoptr i32 %iptr to i8* | 858 %ptr = inttoptr i32 %iptr to i8* |
876 %ignored = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr) | 859 %ignored = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr) |
877 ret i32 0 | 860 ret i32 0 |
878 } | 861 } |
879 ; CHECK-LABEL: test_atomic_is_lock_free_ignored | 862 ; CHECK-LABEL: test_atomic_is_lock_free_ignored |
880 ; CHECK: mov {{.*}}, 0 | 863 ; CHECK: mov {{.*}}, 0 |
881 ; This can get optimized out, because it's side-effect-free. | 864 ; This can get optimized out, because it's side-effect-free. |
882 ; CHECKO2REM-LABEL: test_atomic_is_lock_free_ignored | 865 ; CHECKO2-LABEL: test_atomic_is_lock_free_ignored |
883 ; CHECKO2REM-NOT: mov {{.*}}, 1 | 866 ; CHECKO2-NOT: mov {{.*}}, 1 |
884 ; CHECKO2REM: mov {{.*}}, 0 | 867 ; CHECKO2: mov {{.*}}, 0 |
885 | 868 |
886 ; TODO(jvoung): at some point we can take advantage of the | 869 ; TODO(jvoung): at some point we can take advantage of the |
887 ; fact that nacl.atomic.is.lock.free will resolve to a constant | 870 ; fact that nacl.atomic.is.lock.free will resolve to a constant |
888 ; (which adds DCE opportunities). Once we optimize, the test expectations | 871 ; (which adds DCE opportunities). Once we optimize, the test expectations |
889 ; for this case should change. | 872 ; for this case should change. |
890 define i32 @test_atomic_is_lock_free_can_dce(i32 %iptr, i32 %x, i32 %y) { | 873 define i32 @test_atomic_is_lock_free_can_dce(i32 %iptr, i32 %x, i32 %y) { |
891 entry: | 874 entry: |
892 %ptr = inttoptr i32 %iptr to i8* | 875 %ptr = inttoptr i32 %iptr to i8* |
893 %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr) | 876 %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr) |
894 %i_ext = zext i1 %i to i32 | 877 %i_ext = zext i1 %i to i32 |
895 %cmp = icmp eq i32 %i_ext, 1 | 878 %cmp = icmp eq i32 %i_ext, 1 |
896 br i1 %cmp, label %lock_free, label %not_lock_free | 879 br i1 %cmp, label %lock_free, label %not_lock_free |
897 lock_free: | 880 lock_free: |
898 ret i32 %i_ext | 881 ret i32 %i_ext |
899 | 882 |
900 not_lock_free: | 883 not_lock_free: |
901 %z = add i32 %x, %y | 884 %z = add i32 %x, %y |
902 ret i32 %z | 885 ret i32 %z |
903 } | 886 } |
904 ; CHECK-LABEL: test_atomic_is_lock_free_can_dce | 887 ; CHECK-LABEL: test_atomic_is_lock_free_can_dce |
905 ; CHECK: mov {{.*}}, 1 | 888 ; CHECK: mov {{.*}}, 1 |
906 ; CHECK: ret | 889 ; CHECK: ret |
907 ; CHECK: add | 890 ; CHECK: add |
908 ; CHECK: ret | 891 ; CHECK: ret |
909 | 892 |
910 ; ERRORS-NOT: ICE translation error | 893 ; ERRORS-NOT: ICE translation error |
911 ; DUMP-NOT: SZ | 894 ; DUMP-NOT: SZ |
OLD | NEW |