Subzero: Add a peephole to fuse cmpxchg w/ later cmp+branch.

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s --check-prefix=CHECKO2REM
+; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s --check-prefix=CHECKO2
 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
 ; RUN: %llvm2ice -O2 --verbose none %s \
 ; RUN:               | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj
 ; RUN: %llvm2ice -Om1 --verbose none %s \
 ; RUN:               | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj
 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
 ; RUN:                           | FileCheck --check-prefix=DUMP %s
 
@@ skipping 792 matching lines @@
   ret i64 0
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64_ignored
 ; CHECK: push ebx
 ; CHECK-DAG: mov edx
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}]
 
-define i32 @test_atomic_cmpxchg_32_loop(i32 %iptr, i32 %expected, i32 %desired) {
-entry:
-  br label %loop
-
-loop:
-  %cmp = phi i32 [ %expected, %entry ], [ %old, %loop ]
-  %ptr = inttoptr i32 %iptr to i32*
-  %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %cmp,
-                                                i32 %desired, i32 6, i32 6)
-  %success = icmp eq i32 %cmp, %old
-  br i1 %success, label %done, label %loop
-
-done:
-  ret i32 %old
-}
-; CHECK-LABEL: test_atomic_cmpxchg_32_loop
-
 ;;;; Fence and is-lock-free.
 
 define void @test_atomic_fence() {
 entry:
   call void @llvm.nacl.atomic.fence(i32 6)
   ret void
 }
 ; CHECK-LABEL: test_atomic_fence
 ; CHECK: mfence
 
@@ skipping 27 matching lines @@
 
 define i32 @test_atomic_is_lock_free_ignored(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i8*
   %ignored = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
   ret i32 0
 }
 ; CHECK-LABEL: test_atomic_is_lock_free_ignored
 ; CHECK: mov {{.*}}, 0
 ; This can get optimized out, because it's side-effect-free.
-; CHECKO2REM-LABEL: test_atomic_is_lock_free_ignored
-; CHECKO2REM-NOT: mov {{.*}}, 1
-; CHECKO2REM: mov {{.*}}, 0
+; CHECKO2-LABEL: test_atomic_is_lock_free_ignored
+; CHECKO2-NOT: mov {{.*}}, 1
+; CHECKO2: mov {{.*}}, 0
 
 ; TODO(jvoung): at some point we can take advantage of the
 ; fact that nacl.atomic.is.lock.free will resolve to a constant
 ; (which adds DCE opportunities). Once we optimize, the test expectations
 ; for this case should change.
 define i32 @test_atomic_is_lock_free_can_dce(i32 %iptr, i32 %x, i32 %y) {
 entry:
   %ptr = inttoptr i32 %iptr to i8*
   %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
   %i_ext = zext i1 %i to i32
   %cmp = icmp eq i32 %i_ext, 1
   br i1 %cmp, label %lock_free, label %not_lock_free
 lock_free:
   ret i32 %i_ext
 
 not_lock_free:
   %z = add i32 %x, %y
   ret i32 %z
 }
 ; CHECK-LABEL: test_atomic_is_lock_free_can_dce
 ; CHECK: mov {{.*}}, 1
 ; CHECK: ret
 ; CHECK: add
 ; CHECK: ret
 
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ