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| 1 ; This file checks support for comparing vector values with the fcmp |
| 2 ; instruction. |
| 3 |
| 4 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s |
| 5 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s |
| 6 ; RUN: %llvm2ice -O2 --verbose none %s \ |
| 7 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj |
| 8 ; RUN: %llvm2ice -Om1 --verbose none %s \ |
| 9 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj |
| 10 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s |
| 11 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s |
| 12 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ |
| 13 ; RUN: | FileCheck --check-prefix=DUMP %s |
| 14 |
| 15 ; Check that sext elimination occurs when the result of the comparison |
| 16 ; instruction is alrady sign extended. Sign extension to 4 x i32 uses |
| 17 ; the pslld instruction. |
| 18 define <4 x i32> @sextElimination(<4 x float> %a, <4 x float> %b) { |
| 19 entry: |
| 20 %res.trunc = fcmp oeq <4 x float> %a, %b |
| 21 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 22 ret <4 x i32> %res |
| 23 ; CHECK-LABEL: sextElimination: |
| 24 ; CHECK: cmpeqps |
| 25 ; CHECK-NOT: pslld |
| 26 } |
| 27 |
| 28 define <4 x i32> @fcmpFalseVector(<4 x float> %a, <4 x float> %b) { |
| 29 entry: |
| 30 %res.trunc = fcmp false <4 x float> %a, %b |
| 31 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 32 ret <4 x i32> %res |
| 33 ; CHECK-LABEL: fcmpFalseVector: |
| 34 ; CHECK: pxor |
| 35 } |
| 36 |
| 37 define <4 x i32> @fcmpOeqVector(<4 x float> %a, <4 x float> %b) { |
| 38 entry: |
| 39 %res.trunc = fcmp oeq <4 x float> %a, %b |
| 40 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 41 ret <4 x i32> %res |
| 42 ; CHECK-LABEL: fcmpOeqVector: |
| 43 ; CHECK: cmpeqps |
| 44 } |
| 45 |
| 46 define <4 x i32> @fcmpOgeVector(<4 x float> %a, <4 x float> %b) { |
| 47 entry: |
| 48 %res.trunc = fcmp oge <4 x float> %a, %b |
| 49 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 50 ret <4 x i32> %res |
| 51 ; CHECK-LABEL: fcmpOgeVector: |
| 52 ; CHECK: cmpleps |
| 53 } |
| 54 |
| 55 define <4 x i32> @fcmpOgtVector(<4 x float> %a, <4 x float> %b) { |
| 56 entry: |
| 57 %res.trunc = fcmp ogt <4 x float> %a, %b |
| 58 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 59 ret <4 x i32> %res |
| 60 ; CHECK-LABEL: fcmpOgtVector: |
| 61 ; CHECK: cmpltps |
| 62 } |
| 63 |
| 64 define <4 x i32> @fcmpOleVector(<4 x float> %a, <4 x float> %b) { |
| 65 entry: |
| 66 %res.trunc = fcmp ole <4 x float> %a, %b |
| 67 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 68 ret <4 x i32> %res |
| 69 ; CHECK-LABEL: fcmpOleVector: |
| 70 ; CHECK: cmpleps |
| 71 } |
| 72 |
| 73 define <4 x i32> @fcmpOltVector(<4 x float> %a, <4 x float> %b) { |
| 74 entry: |
| 75 %res.trunc = fcmp olt <4 x float> %a, %b |
| 76 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 77 ret <4 x i32> %res |
| 78 ; CHECK-LABEL: fcmpOltVector: |
| 79 ; CHECK: cmpltps |
| 80 } |
| 81 |
| 82 define <4 x i32> @fcmpOneVector(<4 x float> %a, <4 x float> %b) { |
| 83 entry: |
| 84 %res.trunc = fcmp one <4 x float> %a, %b |
| 85 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 86 ret <4 x i32> %res |
| 87 ; CHECK-LABEL: fcmpOneVector: |
| 88 ; CHECK: cmpneqps |
| 89 ; CHECK: cmpordps |
| 90 ; CHECK: pand |
| 91 } |
| 92 |
| 93 define <4 x i32> @fcmpOrdVector(<4 x float> %a, <4 x float> %b) { |
| 94 entry: |
| 95 %res.trunc = fcmp ord <4 x float> %a, %b |
| 96 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 97 ret <4 x i32> %res |
| 98 ; CHECK-LABEL: fcmpOrdVector: |
| 99 ; CHECK: cmpordps |
| 100 } |
| 101 |
| 102 define <4 x i32> @fcmpTrueVector(<4 x float> %a, <4 x float> %b) { |
| 103 entry: |
| 104 %res.trunc = fcmp true <4 x float> %a, %b |
| 105 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 106 ret <4 x i32> %res |
| 107 ; CHECK-LABEL: fcmpTrueVector: |
| 108 ; CHECK: pcmpeqd |
| 109 } |
| 110 |
| 111 define <4 x i32> @fcmpUeqVector(<4 x float> %a, <4 x float> %b) { |
| 112 entry: |
| 113 %res.trunc = fcmp ueq <4 x float> %a, %b |
| 114 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 115 ret <4 x i32> %res |
| 116 ; CHECK-LABEL: fcmpUeqVector: |
| 117 ; CHECK: cmpeqps |
| 118 ; CHECK: cmpunordps |
| 119 ; CHECK: por |
| 120 } |
| 121 |
| 122 define <4 x i32> @fcmpUgeVector(<4 x float> %a, <4 x float> %b) { |
| 123 entry: |
| 124 %res.trunc = fcmp uge <4 x float> %a, %b |
| 125 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 126 ret <4 x i32> %res |
| 127 ; CHECK-LABEL: fcmpUgeVector: |
| 128 ; CHECK: cmpnltps |
| 129 } |
| 130 |
| 131 define <4 x i32> @fcmpUgtVector(<4 x float> %a, <4 x float> %b) { |
| 132 entry: |
| 133 %res.trunc = fcmp ugt <4 x float> %a, %b |
| 134 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 135 ret <4 x i32> %res |
| 136 ; CHECK-LABEL: fcmpUgtVector: |
| 137 ; CHECK: cmpnleps |
| 138 } |
| 139 |
| 140 define <4 x i32> @fcmpUleVector(<4 x float> %a, <4 x float> %b) { |
| 141 entry: |
| 142 %res.trunc = fcmp ule <4 x float> %a, %b |
| 143 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 144 ret <4 x i32> %res |
| 145 ; CHECK-LABEL: fcmpUleVector: |
| 146 ; CHECK: cmpnltps |
| 147 } |
| 148 |
| 149 define <4 x i32> @fcmpUltVector(<4 x float> %a, <4 x float> %b) { |
| 150 entry: |
| 151 %res.trunc = fcmp ult <4 x float> %a, %b |
| 152 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 153 ret <4 x i32> %res |
| 154 ; CHECK-LABEL: fcmpUltVector: |
| 155 ; CHECK: cmpnleps |
| 156 } |
| 157 |
| 158 define <4 x i32> @fcmpUneVector(<4 x float> %a, <4 x float> %b) { |
| 159 entry: |
| 160 %res.trunc = fcmp une <4 x float> %a, %b |
| 161 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 162 ret <4 x i32> %res |
| 163 ; CHECK-LABEL: fcmpUneVector: |
| 164 ; CHECK: cmpneqps |
| 165 } |
| 166 |
| 167 define <4 x i32> @fcmpUnoVector(<4 x float> %a, <4 x float> %b) { |
| 168 entry: |
| 169 %res.trunc = fcmp uno <4 x float> %a, %b |
| 170 %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 171 ret <4 x i32> %res |
| 172 ; CHECK-LABEL: fcmpUnoVector: |
| 173 ; CHECK: cmpunordps |
| 174 } |
| 175 |
| 176 ; ERRORS-NOT: ICE translation error |
| 177 ; DUMP-NOT: SZ |
| 178 |
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