Use movss to implement insertelement when elements = 4 and index = 0.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 2147 matching lines @@
   // TODO(wala): Determine the best lowering sequences for each type.
   if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Lower extractelement operations where the element is 32 bits
     // wide with pshufd.
     // TODO(wala): SSE4.1 has extractps and pextrd
     //
     // ALIGNHACK: Force vector operands to registers in instructions that
     // require aligned memory operands until support for stack alignment
     // is implemented.
 #define ALIGN_HACK(Vect) legalizeToVar((Vect))
-    Operand *T = NULL;
+    Variable *T = NULL;
     if (Index) {
       // The shuffle only needs to occur if the element to be extracted
       // is not at the lowest index.
       Constant *Mask = Ctx->getConstantInt(IceType_i8, Index);
       T = makeReg(Ty);
-      _pshufd(llvm::cast<Variable>(T), ALIGN_HACK(SourceVectOperand), Mask);
+      _pshufd(T, ALIGN_HACK(SourceVectOperand), Mask);
     } else {
-      // TODO(wala): If SourceVectOperand is in memory, express it as
-      // mem32 so that the call to legalizeToVar() is made unnecessary.
-      // _movd and _movss only take mem32 memory operands.
       T = legalizeToVar(SourceVectOperand);
     }
 
     if (InVectorElementTy == IceType_i32) {
       _movd(ExtractedElement, T);
-    } else { // InVectorElementTy == IceType_f32
-      // TODO: _mov should be able to be used here.
+    } else { // Ty == Icetype_f32
+      // TODO(wala): _movss is only used here because _mov does not
+      // allow a vector source and a scalar destination.  _mov should be
+      // able to be used here.
+      // _movss is a binary instruction, so the FakeDef is needed to
+      // keep the live range analysis consistent.
+      Context.insert(InstFakeDef::create(Func, ExtractedElement));
       _movss(ExtractedElement, T);
     }
 #undef ALIGN_HACK
   } else if (Ty == IceType_v8i16 || Ty == IceType_v8i1) {
     Constant *Mask = Ctx->getConstantInt(IceType_i8, Index);
     _pextrw(ExtractedElement, legalizeToVar(SourceVectOperand), Mask);
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
     // Spill the value to a stack slot and do the extraction in memory.
     // TODO(wala): SSE4.1 has pextrb.
@@ skipping 318 matching lines @@
 }
 
 void TargetX8632::lowerInsertElement(const InstInsertElement *Inst) {
   Operand *SourceVectOperand = Inst->getSrc(0);
   Operand *ElementToInsert = Inst->getSrc(1);
   ConstantInteger *ElementIndex =
       llvm::dyn_cast<ConstantInteger>(Inst->getSrc(2));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
   unsigned Index = ElementIndex->getValue();
+  assert(Index < typeNumElements(SourceVectOperand->getType()));
 
   Type Ty = SourceVectOperand->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = getInVectorElementType(Ty);
 
   if (ElementTy == IceType_i1) {
     // Expand the element to the appropriate size for it to be inserted
     // in the vector.
     Variable *Expanded =
         Func->makeVariable(InVectorElementTy, Context.getNode());
     InstCast *Cast =
         InstCast::create(Func, InstCast::Zext, Expanded, ElementToInsert);
     lowerCast(Cast);
     ElementToInsert = Expanded;
   }
 
   if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
-    // Lower insertelement with 32-bit wide elements using shufps.
+    // Lower insertelement with 32-bit wide elements using shufps or
+    // movss.
     // TODO(wala): SSE4.1 has pinsrd and insertps.
     Variable *Element = NULL;
     if (InVectorElementTy == IceType_f32) {
       // Element will be in an XMM register since it is floating point.
       Element = legalizeToVar(ElementToInsert);
     } else {
       // Copy an integer to an XMM register.
       Operand *T = legalize(ElementToInsert, Legal_Reg | Legal_Mem);
       Element = makeReg(Ty);
       _movd(Element, T);
     }
 
+    if (Index == 0) {
+      Variable *T = makeReg(Ty);
+      _movp(T, SourceVectOperand);
+      _movss(T, Element);
+      _movp(Inst->getDest(), T);
+      return;
+    }
+
     // shufps treats the source and desination operands as vectors of
     // four doublewords.  The destination's two high doublewords are
     // selected from the source operand and the two low doublewords are
     // selected from the (original value of) the destination operand.
     // An insertelement operation can be effected with a sequence of two
     // shufps operations with appropriate masks.  In all cases below,
     // Element[0] is being inserted into SourceVectOperand.  Indices are
     // ordered from left to right.
     //
-    // insertelement into index 0 (result is stored in Element):
-    //   Element := Element[0, 0] SourceVectOperand[0, 1]
-    //   Element := Element[0, 3] SourceVectOperand[2, 3]
-    //
     // insertelement into index 1 (result is stored in Element):
     //   Element := Element[0, 0] SourceVectOperand[0, 0]
     //   Element := Element[3, 0] SourceVectOperand[2, 3]
     //
     // insertelement into index 2 (result is stored in T):
     //   T := SourceVectOperand
     //   Element := Element[0, 0] T[0, 3]
     //   T := T[0, 1] Element[0, 3]
     //
     // insertelement into index 3 (result is stored in T):
     //   T := SourceVectOperand
     //   Element := Element[0, 0] T[0, 2]
     //   T := T[0, 1] Element[3, 0]
-    const unsigned char Mask1[4] = {64, 0, 192, 128};
-    const unsigned char Mask2[4] = {236, 227, 196, 52};
+    const unsigned char Mask1[3] = {0, 192, 128};
+    const unsigned char Mask2[3] = {227, 196, 52};
 
-    Constant *Mask1Constant = Ctx->getConstantInt(IceType_i8, Mask1[Index]);
-    Constant *Mask2Constant = Ctx->getConstantInt(IceType_i8, Mask2[Index]);
+    Constant *Mask1Constant = Ctx->getConstantInt(IceType_i8, Mask1[Index - 1]);
+    Constant *Mask2Constant = Ctx->getConstantInt(IceType_i8, Mask2[Index - 1]);
 
     // ALIGNHACK: Force vector operands to registers in instructions that
     // require aligned memory operands until support for stack alignment
     // is implemented.
 #define ALIGN_HACK(Vect) legalizeToVar((Vect))
-    if (Index < 2) {
+    if (Index == 1) {
       SourceVectOperand = ALIGN_HACK(SourceVectOperand);
       _shufps(Element, SourceVectOperand, Mask1Constant);
       _shufps(Element, SourceVectOperand, Mask2Constant);
       _movp(Inst->getDest(), Element);
     } else {
       Variable *T = makeReg(Ty);
       _movp(T, SourceVectOperand);
       _shufps(Element, T, Mask1Constant);
       _shufps(T, Element, Mask2Constant);
       _movp(Inst->getDest(), T);
@@ skipping 1409 matching lines @@
     for (SizeT i = 0; i < Size; ++i) {
       Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n";
     }
     Str << "\t.size\t" << MangledName << ", " << Size << "\n";
   }
   Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName
       << "\n";
 }
 
 } // end of namespace Ice