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Side by Side Diff: arch/arm/mach-tegra/common.c

Issue 4120008: CHROMIUM: ARM: Tegra: Clean up 3D clock init WAR. (Closed) Base URL: http://git.chromium.org/git/kernel-next.git
Patch Set: Created 10 years, 1 month ago
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1 /* 1 /*
2 * arch/arm/mach-tegra/common.c 2 * arch/arm/mach-tegra/common.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * 5 *
6 * Author: 6 * Author:
7 * Colin Cross <ccross@android.com> 7 * Colin Cross <ccross@android.com>
8 * 8 *
9 * This software is licensed under the terms of the GNU General Public 9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and 10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms. 11 * may be copied, distributed, and modified under those terms.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 */ 18 */
19 19
20 #include <linux/init.h> 20 #include <linux/init.h>
21 #include <linux/io.h> 21 #include <linux/io.h>
22 #include <linux/clk.h> 22 #include <linux/clk.h>
23 #include <linux/delay.h> 23 #include <linux/delay.h>
24 24
25 #include <asm/hardware/cache-l2x0.h> 25 #include <asm/hardware/cache-l2x0.h>
26 26
27 #include <mach/iomap.h> 27 #include <mach/iomap.h>
28 #include <mach/clk.h>
28 #include <mach/dma.h> 29 #include <mach/dma.h>
30 #include <mach/powergate.h>
29 #include <mach/system.h> 31 #include <mach/system.h>
30 32
31 #include "board.h" 33 #include "board.h"
32 #include "clock.h" 34 #include "clock.h"
33 #include "fuse.h" 35 #include "fuse.h"
34 36
35 void (*tegra_reset)(char mode, const char *cmd); 37 void (*tegra_reset)(char mode, const char *cmd);
36 38
37 static __initdata struct tegra_clk_init_table common_clk_init_table[] = { 39 static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
38 /* name parent rate enabled */ 40 /* name parent rate enabled */
(...skipping 20 matching lines...) Expand all
59 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; 61 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
60 62
61 writel(0x331, p + L2X0_TAG_LATENCY_CTRL); 63 writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
62 writel(0x441, p + L2X0_DATA_LATENCY_CTRL); 64 writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
63 65
64 l2x0_init(p, 0x6C080001, 0x8200c3fe); 66 l2x0_init(p, 0x6C080001, 0x8200c3fe);
65 #endif 67 #endif
66 68
67 } 69 }
68 70
69 void __init tegra_common_init(void) 71 void __init tegra_common_init(struct tegra_clk_init_table *board_clk_init_table)
70 { 72 {
73 struct clk *clk;
74
71 tegra_init_fuse(); 75 tegra_init_fuse();
72 tegra_init_clock(); 76 tegra_init_clock();
73 tegra_clk_init_from_table(common_clk_init_table); 77 tegra_clk_init_from_table(common_clk_init_table);
78 tegra_clk_init_from_table(board_clk_init_table);
79
80 /* HACK: reset 3d clock */
81 clk = clk_get_sys("3d", NULL);
82 tegra_powergate_power_off(TEGRA_POWERGATE_3D);
83 tegra_periph_reset_assert(clk);
84 tegra_powergate_power_on(TEGRA_POWERGATE_3D);
85 clk_enable(clk);
86 udelay(10);
87 tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
88 tegra_periph_reset_deassert(clk);
89 clk_put(clk);
90
74 tegra_init_cache(); 91 tegra_init_cache();
75 #ifdef CONFIG_TEGRA_SYSTEM_DMA 92 #ifdef CONFIG_TEGRA_SYSTEM_DMA
76 tegra_dma_init(); 93 tegra_dma_init();
77 #endif 94 #endif
78 } 95 }
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