Fix legalization of source operand to bsr and bsf.

tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll

 ; This tests the NaCl intrinsics not related to atomic operations.
 
 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
 
 ; Do another run w/ O2 and a different check-prefix (otherwise O2 and Om1
 ; share the same "CHECK" prefix). This separate run helps check that
 ; some code is optimized out.
 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s --check-prefix=CHECKO2REM
 
-; TODO: The next two lines cause this test to fail.
-; RUIN: %llvm2ice -O2 --verbose none %s | llvm-mc -x86-asm-syntax=intel
-; RUIN: %llvm2ice -Om1 --verbose none %s | llvm-mc -x86-asm-syntax=intel
+; RUN: %llvm2ice -O2 --verbose none %s | llvm-mc -x86-asm-syntax=intel
+; RUN: %llvm2ice -Om1 --verbose none %s | llvm-mc -x86-asm-syntax=intel
 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
 ; RUN:                           | FileCheck --check-prefix=DUMP %s
 
 declare i8* @llvm.nacl.read.tp()
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
 declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
 declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i32, i1)
 declare void @llvm.nacl.longjmp(i8*, i32)
@@ skipping 279 matching lines @@
 ; CHECK: mov [[REG_RES:e.*]], 63
 ; CHECK: cmovne [[REG_RES]], [[REG_TMP]]
 ; CHECK: xor [[REG_RES]], 31
 
 define i32 @test_ctlz_32_const() {
 entry:
   %r = call i32 @llvm.ctlz.i32(i32 123456, i1 0)
   ret i32 %r
 }
 ; Could potentially constant fold this, but the front-end should have done that.
+; The dest operand must be a register and the source operand must be a register
+; or memory.
 ; CHECK-LABEL: test_ctlz_32_const
-; CHECK: bsr
+; CHECK: bsr e{{.*}}, {{.*}}e{{.*}}
 
 define i32 @test_ctlz_32_ignored(i32 %x) {
 entry:
   %ignored = call i32 @llvm.ctlz.i32(i32 %x, i1 0)
   ret i32 1
 }
 ; CHECKO2REM-LABEL: test_ctlz_32_ignored
 ; CHECKO2REM-NOT: bsr
 
 define i64 @test_ctlz_64(i64 %x) {
@@ skipping 14 matching lines @@
 ; CHECK: cmove [[REG_RES2]], [[REG_RES1]]
 ; CHECK: mov {{.*}}, 0
 
 define i32 @test_ctlz_64_const(i64 %x) {
 entry:
   %r = call i64 @llvm.ctlz.i64(i64 123456789012, i1 0)
   %r2 = trunc i64 %r to i32
   ret i32 %r2
 }
 ; CHECK-LABEL: test_ctlz_64_const
-; CHECK: bsr
-; CHECK: bsr
+; CHECK: bsr e{{.*}}, {{.*}}e{{.*}}
+; CHECK: bsr e{{.*}}, {{.*}}e{{.*}}
+
 
 define i32 @test_ctlz_64_ignored(i64 %x) {
 entry:
   %ignored = call i64 @llvm.ctlz.i64(i64 1234567890, i1 0)
   ret i32 2
 }
 ; CHECKO2REM-LABEL: test_ctlz_64_ignored
 ; CHECKO2REM-NOT: bsr
 
 define i32 @test_cttz_32(i32 %x) {
@@ skipping 91 matching lines @@
 }
 ; CHECK-LABEL: test_stacksave_multiple
 ; At least 3 copies of esp, but probably more from having to do the allocas.
 ; CHECK: mov {{.*}}, esp
 ; CHECK: mov {{.*}}, esp
 ; CHECK: mov {{.*}}, esp
 ; CHECK: mov esp, {{.*}}
 
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ