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Issue 402923002: [Arm]: Assert that movw/movt is only emitted for Armv7 targets (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 5 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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1488 emit(link); 1488 emit(link);
1489 nop(dst.code()); 1489 nop(dst.code());
1490 if (!CpuFeatures::IsSupported(ARMv7)) { 1490 if (!CpuFeatures::IsSupported(ARMv7)) {
1491 nop(dst.code()); 1491 nop(dst.code());
1492 } 1492 }
1493 } 1493 }
1494 } 1494 }
1495 1495
1496 1496
1497 void Assembler::movw(Register reg, uint32_t immediate, Condition cond) { 1497 void Assembler::movw(Register reg, uint32_t immediate, Condition cond) {
1498 ASSERT(CpuFeatures::IsSupported(ARMv7));
1498 emit(cond | 0x30*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate)); 1499 emit(cond | 0x30*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate));
1499 } 1500 }
1500 1501
1501 1502
1502 void Assembler::movt(Register reg, uint32_t immediate, Condition cond) { 1503 void Assembler::movt(Register reg, uint32_t immediate, Condition cond) {
1504 ASSERT(CpuFeatures::IsSupported(ARMv7));
1503 emit(cond | 0x34*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate)); 1505 emit(cond | 0x34*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate));
1504 } 1506 }
1505 1507
1506 1508
1507 void Assembler::bic(Register dst, Register src1, const Operand& src2, 1509 void Assembler::bic(Register dst, Register src1, const Operand& src2,
1508 SBit s, Condition cond) { 1510 SBit s, Condition cond) {
1509 addrmod1(cond | BIC | s, src1, dst, src2); 1511 addrmod1(cond | BIC | s, src1, dst, src2);
1510 } 1512 }
1511 1513
1512 1514
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3731 assm->instr_at_put( 3733 assm->instr_at_put(
3732 rinfo.pc(), Assembler::SetLdrRegisterImmediateOffset(instr, offset)); 3734 rinfo.pc(), Assembler::SetLdrRegisterImmediateOffset(instr, offset));
3733 } 3735 }
3734 } 3736 }
3735 } 3737 }
3736 3738
3737 3739
3738 } } // namespace v8::internal 3740 } } // namespace v8::internal
3739 3741
3740 #endif // V8_TARGET_ARCH_ARM 3742 #endif // V8_TARGET_ARCH_ARM
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