Lower insertelement and extractelement.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstX8632 and OperandX8632 classes,
@@ skipping 24 matching lines @@
   };
 const size_t InstX8632BrAttributesSize =
     llvm::array_lengthof(InstX8632BrAttributes);
 
 const struct TypeX8632Attributes_ {
   const char *CvtString;   // i (integer), s (single FP), d (double FP)
   const char *SdSsString;  // ss, sd, or <blank>
   const char *PackString;  // b, w, d, or <blank>
   const char *WidthString; // {byte,word,dword,qword} ptr
 } TypeX8632Attributes[] = {
-#define X(tag, cvt, sdss, pack, width)                                         \
+#define X(tag, elementty, cvt, sdss, pack, width)                              \
   { cvt, "" sdss, pack, width }                                                \
   ,
     ICETYPEX8632_TABLE
 #undef X
   };
 const size_t TypeX8632AttributesSize =
     llvm::array_lengthof(TypeX8632Attributes);
 
 const char *InstX8632SegmentRegNames[] = {
 #define X(val, name) name,
@@ skipping 376 matching lines @@
     if (ShiftReg && ShiftReg->getRegNum() == TargetX8632::Reg_ecx) {
       Str << "cl";
       EmittedSrc1 = true;
     }
   }
   if (!EmittedSrc1)
     Inst->getSrc(1)->emit(Func);
   Str << "\n";
 }
 
+
+// Unary ops
 template <> const char *InstX8632Bsf::Opcode = "bsf";
 template <> const char *InstX8632Bsr::Opcode = "bsr";
+template <> const char *InstX8632Lea::Opcode = "lea";
+template <> const char *InstX8632Movd::Opcode = "movd";
+template <> const char *InstX8632Movss::Opcode = "movss";
 template <> const char *InstX8632Sqrtss::Opcode = "sqrtss";
+// Binary ops
 template <> const char *InstX8632Add::Opcode = "add";
 template <> const char *InstX8632Addps::Opcode = "addps";
 template <> const char *InstX8632Adc::Opcode = "adc";
 template <> const char *InstX8632Addss::Opcode = "addss";
 template <> const char *InstX8632Sub::Opcode = "sub";
 template <> const char *InstX8632Subps::Opcode = "subps";
 template <> const char *InstX8632Subss::Opcode = "subss";
 template <> const char *InstX8632Psub::Opcode = "psub";
 template <> const char *InstX8632Sbb::Opcode = "sbb";
 template <> const char *InstX8632And::Opcode = "and";
 template <> const char *InstX8632Pand::Opcode = "pand";
 template <> const char *InstX8632Or::Opcode = "or";
 template <> const char *InstX8632Xor::Opcode = "xor";
 template <> const char *InstX8632Pxor::Opcode = "pxor";
 template <> const char *InstX8632Imul::Opcode = "imul";
 template <> const char *InstX8632Mulps::Opcode = "mulps";
 template <> const char *InstX8632Mulss::Opcode = "mulss";
 template <> const char *InstX8632Div::Opcode = "div";
 template <> const char *InstX8632Divps::Opcode = "divps";
 template <> const char *InstX8632Idiv::Opcode = "idiv";
 template <> const char *InstX8632Divss::Opcode = "divss";
 template <> const char *InstX8632Shl::Opcode = "shl";
 template <> const char *InstX8632Psll::Opcode = "psll";
 template <> const char *InstX8632Shr::Opcode = "shr";
 template <> const char *InstX8632Sar::Opcode = "sar";
 template <> const char *InstX8632Psra::Opcode = "psra";
 template <> const char *InstX8632Pcmpeq::Opcode = "pcmpeq";
 template <> const char *InstX8632Pcmpgt::Opcode = "pcmpgt";
+// Ternary ops
+template <> const char *InstX8632Shufps::Opcode = "shufps";
+template <> const char *InstX8632Pinsrw::Opcode = "pinsrw";
+// Three address ops
+template <> const char *InstX8632Pextrw::Opcode = "pextrw";
+template <> const char *InstX8632Pshufd::Opcode = "pshufd";
 
 template <> void InstX8632Sqrtss::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Type Ty = getSrc(0)->getType();
   assert(Ty == IceType_f32 || Ty == IceType_f64);
   Str << "\tsqrt" << TypeX8632Attributes[Ty].SdSsString << "\t";
   getDest()->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
@@ skipping 21 matching lines @@
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Divss::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "div%s",
            TypeX8632Attributes[getDest()->getType()].SdSsString);
   emitTwoAddress(buf, this, Func);
 }
 
+template <> void InstX8632Div::emit(const Cfg *Func) const {
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 3);
+  Str << "\t" << Opcode << "\t";
+  getSrc(1)->emit(Func);
+  Str << "\n";
+}
+
+template <> void InstX8632Idiv::emit(const Cfg *Func) const {
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 3);
+  Str << "\t" << Opcode << "\t";
+  getSrc(1)->emit(Func);
+  Str << "\n";
+}
+
 template <> void InstX8632Imul::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   if (getDest()->getType() == IceType_i8) {
     // The 8-bit version of imul only allows the form "imul r/m8".
     Variable *Src0 = llvm::dyn_cast<Variable>(getSrc(0));
     assert(Src0 && Src0->getRegNum() == TargetX8632::Reg_eax);
     Str << "\timul\t";
     getSrc(1)->emit(Func);
     Str << "\n";
@@ skipping 292 matching lines @@
 }
 
 void InstX8632StoreQ::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "storeq." << getSrc(0)->getType() << " ";
   getSrc(1)->dump(Func);
   Str << ", ";
   getSrc(0)->dump(Func);
 }
 
+template <> void InstX8632Lea::emit(const Cfg *Func) const {
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 1);
+  assert(getDest()->hasReg());
+  Str << "\tlea\t";
+  getDest()->emit(Func);
+  Str << ", ";
+  Operand *Src0 = getSrc(0);
+  if (Variable *VSrc0 = llvm::dyn_cast<Variable>(Src0)) {
+    Type Ty = VSrc0->getType();
+    // lea on x86-32 doesn't accept mem128 operands, so cast VSrc0 to an
+    // acceptable type.
+    VSrc0->asType(isVectorType(Ty) ? IceType_i32 : Ty).emit(Func);
+  } else {
+    Src0->emit(Func);
+  }
+  Str << "\n";
+}
+
 void InstX8632Mov::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Operand *Src = getSrc(0);
   // The llvm-mc assembler using Intel syntax has a bug in which "mov
   // reg, RelocatableConstant" does not generate the right instruction
   // with a relocation.  To work around, we emit "lea reg,
   // [RelocatableConstant]".  Also, the lowering and legalization is
   // changed to allow relocatable constants only in Assign and Call
   // instructions or in Mem operands.  TODO(stichnot): remove LEAHACK
@@ skipping 178 matching lines @@
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Pcmpgt::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "pcmpgt%s",
            TypeX8632Attributes[getDest()->getType()].PackString);
   emitTwoAddress(buf, this, Func);
 }
 
+template <> void InstX8632Pextrw::emit(const Cfg *Func) const {
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 2);
+  Str << "\t" << Opcode << "\t";
+  Variable *Dest = getDest();
+  assert(Dest->hasReg() && Dest->getType() == IceType_i16);
+  // pextrw takes r32 dest.
+  Dest->asType(IceType_i32).emit(Func);
+  Str << ", ";
+  getSrc(0)->emit(Func);
+  Str << ", ";
+  getSrc(1)->emit(Func);
+  Str << "\n";
+}
+
+template <> void InstX8632Pinsrw::emit(const Cfg *Func) const {
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(getSrcSize() == 3);
+  Str << "\t" << Opcode << "\t";
+  getDest()->emit(Func);
+  Str << ", ";
+  Operand *Src1 = getSrc(1);
+  if (Variable *VSrc1 = llvm::dyn_cast<Variable>(Src1)) {
+    // If src1 is a register, it should be r32.
+    VSrc1->asType(VSrc1->hasReg() ? IceType_i32 : IceType_i16).emit(Func);
+  } else {
+    Src1->emit(Func);
+  }
+  Str << ", ";
+  getSrc(2)->emit(Func);
+  Str << "\n";
+}
+
 void InstX8632Pop::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 0);
   Str << "\tpop\t";
   getDest()->emit(Func);
   Str << "\n";
 }
 
 void InstX8632Pop::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
@@ skipping 242 matching lines @@
   default:
     Str << "???";
     break;
   }
   Str << "(";
   Var->dump(Func);
   Str << ")";
 }
 
 } // end of namespace Ice