| OLD | NEW |
|---|
| (Empty) | |
| 1 target triple = "i686-pc-linux-gnu" |
| 2 |
| 3 define <4 x float> @insertelement_v4f32(<4 x float> %vec, float %elt, i32 %idx)
{ |
| 4 switch i32 %idx, label %abort [ |
| 5 i32 0, label %idx0 |
| 6 i32 1, label %idx1 |
| 7 i32 2, label %idx2 |
| 8 i32 3, label %idx3 |
| 9 ] |
| 10 idx0: |
| 11 %res0 = insertelement <4 x float> %vec, float %elt, i32 0 |
| 12 ret <4 x float> %res0 |
| 13 idx1: |
| 14 %res1 = insertelement <4 x float> %vec, float %elt, i32 1 |
| 15 ret <4 x float> %res1 |
| 16 idx2: |
| 17 %res2 = insertelement <4 x float> %vec, float %elt, i32 2 |
| 18 ret <4 x float> %res2 |
| 19 idx3: |
| 20 %res3 = insertelement <4 x float> %vec, float %elt, i32 3 |
| 21 ret <4 x float> %res3 |
| 22 abort: |
| 23 unreachable |
| 24 } |
| 25 |
| 26 define <4 x i32> @insertelement_v4i1(<4 x i32> %arg_vec, i64 %elt_arg, i32 %idx)
{ |
| 27 %vec = trunc <4 x i32> %arg_vec to <4 x i1> |
| 28 %elt = trunc i64 %elt_arg to i1 |
| 29 switch i32 %idx, label %abort [ |
| 30 i32 0, label %idx0 |
| 31 i32 1, label %idx1 |
| 32 i32 2, label %idx2 |
| 33 i32 3, label %idx3 |
| 34 ] |
| 35 idx0: |
| 36 %res0_i1 = insertelement <4 x i1> %vec, i1 %elt, i32 0 |
| 37 %res0 = zext <4 x i1> %res0_i1 to <4 x i32> |
| 38 ret <4 x i32> %res0 |
| 39 idx1: |
| 40 %res1_i1 = insertelement <4 x i1> %vec, i1 %elt, i32 1 |
| 41 %res1 = zext <4 x i1> %res1_i1 to <4 x i32> |
| 42 ret <4 x i32> %res1 |
| 43 idx2: |
| 44 %res2_i1 = insertelement <4 x i1> %vec, i1 %elt, i32 2 |
| 45 %res2 = zext <4 x i1> %res2_i1 to <4 x i32> |
| 46 ret <4 x i32> %res2 |
| 47 idx3: |
| 48 %res3_i1 = insertelement <4 x i1> %vec, i1 %elt, i32 3 |
| 49 %res3 = zext <4 x i1> %res3_i1 to <4 x i32> |
| 50 ret <4 x i32> %res3 |
| 51 abort: |
| 52 unreachable |
| 53 } |
| 54 |
| 55 define <8 x i16> @insertelement_v8i1(<8 x i16> %arg_vec, i64 %elt_arg, i32 %idx)
{ |
| 56 %vec = trunc <8 x i16> %arg_vec to <8 x i1> |
| 57 %elt = trunc i64 %elt_arg to i1 |
| 58 switch i32 %idx, label %abort [ |
| 59 i32 0, label %idx0 |
| 60 i32 1, label %idx1 |
| 61 i32 2, label %idx2 |
| 62 i32 3, label %idx3 |
| 63 i32 4, label %idx4 |
| 64 i32 5, label %idx5 |
| 65 i32 6, label %idx6 |
| 66 i32 7, label %idx7 |
| 67 ] |
| 68 idx0: |
| 69 %res0_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 0 |
| 70 %res0 = zext <8 x i1> %res0_i1 to <8 x i16> |
| 71 ret <8 x i16> %res0 |
| 72 idx1: |
| 73 %res1_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 1 |
| 74 %res1 = zext <8 x i1> %res1_i1 to <8 x i16> |
| 75 ret <8 x i16> %res1 |
| 76 idx2: |
| 77 %res2_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 2 |
| 78 %res2 = zext <8 x i1> %res2_i1 to <8 x i16> |
| 79 ret <8 x i16> %res2 |
| 80 idx3: |
| 81 %res3_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 3 |
| 82 %res3 = zext <8 x i1> %res3_i1 to <8 x i16> |
| 83 ret <8 x i16> %res3 |
| 84 idx4: |
| 85 %res4_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 4 |
| 86 %res4 = zext <8 x i1> %res4_i1 to <8 x i16> |
| 87 ret <8 x i16> %res4 |
| 88 idx5: |
| 89 %res5_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 5 |
| 90 %res5 = zext <8 x i1> %res5_i1 to <8 x i16> |
| 91 ret <8 x i16> %res5 |
| 92 idx6: |
| 93 %res6_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 6 |
| 94 %res6 = zext <8 x i1> %res6_i1 to <8 x i16> |
| 95 ret <8 x i16> %res6 |
| 96 idx7: |
| 97 %res7_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 7 |
| 98 %res7 = zext <8 x i1> %res7_i1 to <8 x i16> |
| 99 ret <8 x i16> %res7 |
| 100 abort: |
| 101 unreachable |
| 102 } |
| 103 |
| 104 define <16 x i8> @insertelement_v16i1(<16 x i8> %arg_vec, i64 %elt_arg, i32 %idx
) { |
| 105 %vec = trunc <16 x i8> %arg_vec to <16 x i1> |
| 106 %elt = trunc i64 %elt_arg to i1 |
| 107 switch i32 %idx, label %abort [ |
| 108 i32 0, label %idx0 |
| 109 i32 1, label %idx1 |
| 110 i32 2, label %idx2 |
| 111 i32 3, label %idx3 |
| 112 i32 4, label %idx4 |
| 113 i32 5, label %idx5 |
| 114 i32 6, label %idx6 |
| 115 i32 7, label %idx7 |
| 116 i32 8, label %idx8 |
| 117 i32 9, label %idx9 |
| 118 i32 10, label %idx10 |
| 119 i32 11, label %idx11 |
| 120 i32 12, label %idx12 |
| 121 i32 13, label %idx13 |
| 122 i32 14, label %idx14 |
| 123 i32 15, label %idx15 |
| 124 ] |
| 125 idx0: |
| 126 %res0_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 0 |
| 127 %res0 = zext <16 x i1> %res0_i1 to <16 x i8> |
| 128 ret <16 x i8> %res0 |
| 129 idx1: |
| 130 %res1_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 1 |
| 131 %res1 = zext <16 x i1> %res1_i1 to <16 x i8> |
| 132 ret <16 x i8> %res1 |
| 133 idx2: |
| 134 %res2_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 2 |
| 135 %res2 = zext <16 x i1> %res2_i1 to <16 x i8> |
| 136 ret <16 x i8> %res2 |
| 137 idx3: |
| 138 %res3_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 3 |
| 139 %res3 = zext <16 x i1> %res3_i1 to <16 x i8> |
| 140 ret <16 x i8> %res3 |
| 141 idx4: |
| 142 %res4_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 4 |
| 143 %res4 = zext <16 x i1> %res4_i1 to <16 x i8> |
| 144 ret <16 x i8> %res4 |
| 145 idx5: |
| 146 %res5_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 5 |
| 147 %res5 = zext <16 x i1> %res5_i1 to <16 x i8> |
| 148 ret <16 x i8> %res5 |
| 149 idx6: |
| 150 %res6_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 6 |
| 151 %res6 = zext <16 x i1> %res6_i1 to <16 x i8> |
| 152 ret <16 x i8> %res6 |
| 153 idx7: |
| 154 %res7_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 7 |
| 155 %res7 = zext <16 x i1> %res7_i1 to <16 x i8> |
| 156 ret <16 x i8> %res7 |
| 157 idx8: |
| 158 %res8_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 8 |
| 159 %res8 = zext <16 x i1> %res8_i1 to <16 x i8> |
| 160 ret <16 x i8> %res8 |
| 161 idx9: |
| 162 %res9_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 9 |
| 163 %res9 = zext <16 x i1> %res9_i1 to <16 x i8> |
| 164 ret <16 x i8> %res9 |
| 165 idx10: |
| 166 %res10_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 10 |
| 167 %res10 = zext <16 x i1> %res10_i1 to <16 x i8> |
| 168 ret <16 x i8> %res10 |
| 169 idx11: |
| 170 %res11_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 11 |
| 171 %res11 = zext <16 x i1> %res11_i1 to <16 x i8> |
| 172 ret <16 x i8> %res11 |
| 173 idx12: |
| 174 %res12_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 12 |
| 175 %res12 = zext <16 x i1> %res12_i1 to <16 x i8> |
| 176 ret <16 x i8> %res12 |
| 177 idx13: |
| 178 %res13_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 13 |
| 179 %res13 = zext <16 x i1> %res13_i1 to <16 x i8> |
| 180 ret <16 x i8> %res13 |
| 181 idx14: |
| 182 %res14_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 14 |
| 183 %res14 = zext <16 x i1> %res14_i1 to <16 x i8> |
| 184 ret <16 x i8> %res14 |
| 185 idx15: |
| 186 %res15_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 15 |
| 187 %res15 = zext <16 x i1> %res15_i1 to <16 x i8> |
| 188 ret <16 x i8> %res15 |
| 189 abort: |
| 190 unreachable |
| 191 } |
| 192 |
| 193 define <4 x i32> @insertelement_v4si32(<4 x i32> %vec, i64 %elt_arg, i32 %idx) { |
| 194 entry: |
| 195 %elt = trunc i64 %elt_arg to i32 |
| 196 switch i32 %idx, label %abort [ |
| 197 i32 0, label %idx0 |
| 198 i32 1, label %idx1 |
| 199 i32 2, label %idx2 |
| 200 i32 3, label %idx3 |
| 201 ] |
| 202 idx0: |
| 203 %res0 = insertelement <4 x i32> %vec, i32 %elt, i32 0 |
| 204 ret <4 x i32> %res0 |
| 205 idx1: |
| 206 %res1 = insertelement <4 x i32> %vec, i32 %elt, i32 1 |
| 207 ret <4 x i32> %res1 |
| 208 idx2: |
| 209 %res2 = insertelement <4 x i32> %vec, i32 %elt, i32 2 |
| 210 ret <4 x i32> %res2 |
| 211 idx3: |
| 212 %res3 = insertelement <4 x i32> %vec, i32 %elt, i32 3 |
| 213 ret <4 x i32> %res3 |
| 214 abort: |
| 215 unreachable |
| 216 } |
| 217 |
| 218 define <4 x i32> @insertelement_v4ui32(<4 x i32> %vec, i64 %elt_arg, i32 %idx) { |
| 219 entry: |
| 220 %res = call <4 x i32> @insertelement_v4si32(<4 x i32> %vec, i64 %elt_arg, i32
%idx) |
| 221 ret <4 x i32> %res |
| 222 } |
| 223 |
| 224 define <8 x i16> @insertelement_v8si16(<8 x i16> %vec, i64 %elt_arg, i32 %idx) { |
| 225 entry: |
| 226 %elt = trunc i64 %elt_arg to i16 |
| 227 switch i32 %idx, label %abort [ |
| 228 i32 0, label %idx0 |
| 229 i32 1, label %idx1 |
| 230 i32 2, label %idx2 |
| 231 i32 3, label %idx3 |
| 232 i32 4, label %idx4 |
| 233 i32 5, label %idx5 |
| 234 i32 6, label %idx6 |
| 235 i32 7, label %idx7 |
| 236 ] |
| 237 idx0: |
| 238 %res0 = insertelement <8 x i16> %vec, i16 %elt, i32 0 |
| 239 ret <8 x i16> %res0 |
| 240 idx1: |
| 241 %res1 = insertelement <8 x i16> %vec, i16 %elt, i32 1 |
| 242 ret <8 x i16> %res1 |
| 243 idx2: |
| 244 %res2 = insertelement <8 x i16> %vec, i16 %elt, i32 2 |
| 245 ret <8 x i16> %res2 |
| 246 idx3: |
| 247 %res3 = insertelement <8 x i16> %vec, i16 %elt, i32 3 |
| 248 ret <8 x i16> %res3 |
| 249 idx4: |
| 250 %res4 = insertelement <8 x i16> %vec, i16 %elt, i32 4 |
| 251 ret <8 x i16> %res4 |
| 252 idx5: |
| 253 %res5 = insertelement <8 x i16> %vec, i16 %elt, i32 5 |
| 254 ret <8 x i16> %res5 |
| 255 idx6: |
| 256 %res6 = insertelement <8 x i16> %vec, i16 %elt, i32 6 |
| 257 ret <8 x i16> %res6 |
| 258 idx7: |
| 259 %res7 = insertelement <8 x i16> %vec, i16 %elt, i32 7 |
| 260 ret <8 x i16> %res7 |
| 261 abort: |
| 262 unreachable |
| 263 } |
| 264 |
| 265 define <8 x i16> @insertelement_v8ui16(<8 x i16> %vec, i64 %elt_arg, i32 %idx) { |
| 266 entry: |
| 267 %res = call <8 x i16> @insertelement_v8si16(<8 x i16> %vec, i64 %elt_arg, i32
%idx) |
| 268 ret <8 x i16> %res |
| 269 } |
| 270 |
| 271 define <16 x i8> @insertelement_v16si8(<16 x i8> %vec, i64 %elt_arg, i32 %idx) { |
| 272 entry: |
| 273 %elt = trunc i64 %elt_arg to i8 |
| 274 switch i32 %idx, label %abort [ |
| 275 i32 0, label %idx0 |
| 276 i32 1, label %idx1 |
| 277 i32 2, label %idx2 |
| 278 i32 3, label %idx3 |
| 279 i32 4, label %idx4 |
| 280 i32 5, label %idx5 |
| 281 i32 6, label %idx6 |
| 282 i32 7, label %idx7 |
| 283 i32 8, label %idx8 |
| 284 i32 9, label %idx9 |
| 285 i32 10, label %idx10 |
| 286 i32 11, label %idx11 |
| 287 i32 12, label %idx12 |
| 288 i32 13, label %idx13 |
| 289 i32 14, label %idx14 |
| 290 i32 15, label %idx15 |
| 291 ] |
| 292 idx0: |
| 293 %res0 = insertelement <16 x i8> %vec, i8 %elt, i32 0 |
| 294 ret <16 x i8> %res0 |
| 295 idx1: |
| 296 %res1 = insertelement <16 x i8> %vec, i8 %elt, i32 1 |
| 297 ret <16 x i8> %res1 |
| 298 idx2: |
| 299 %res2 = insertelement <16 x i8> %vec, i8 %elt, i32 2 |
| 300 ret <16 x i8> %res2 |
| 301 idx3: |
| 302 %res3 = insertelement <16 x i8> %vec, i8 %elt, i32 3 |
| 303 ret <16 x i8> %res3 |
| 304 idx4: |
| 305 %res4 = insertelement <16 x i8> %vec, i8 %elt, i32 4 |
| 306 ret <16 x i8> %res4 |
| 307 idx5: |
| 308 %res5 = insertelement <16 x i8> %vec, i8 %elt, i32 5 |
| 309 ret <16 x i8> %res5 |
| 310 idx6: |
| 311 %res6 = insertelement <16 x i8> %vec, i8 %elt, i32 6 |
| 312 ret <16 x i8> %res6 |
| 313 idx7: |
| 314 %res7 = insertelement <16 x i8> %vec, i8 %elt, i32 7 |
| 315 ret <16 x i8> %res7 |
| 316 idx8: |
| 317 %res8 = insertelement <16 x i8> %vec, i8 %elt, i32 8 |
| 318 ret <16 x i8> %res8 |
| 319 idx9: |
| 320 %res9 = insertelement <16 x i8> %vec, i8 %elt, i32 9 |
| 321 ret <16 x i8> %res9 |
| 322 idx10: |
| 323 %res10 = insertelement <16 x i8> %vec, i8 %elt, i32 10 |
| 324 ret <16 x i8> %res10 |
| 325 idx11: |
| 326 %res11 = insertelement <16 x i8> %vec, i8 %elt, i32 11 |
| 327 ret <16 x i8> %res11 |
| 328 idx12: |
| 329 %res12 = insertelement <16 x i8> %vec, i8 %elt, i32 12 |
| 330 ret <16 x i8> %res12 |
| 331 idx13: |
| 332 %res13 = insertelement <16 x i8> %vec, i8 %elt, i32 13 |
| 333 ret <16 x i8> %res13 |
| 334 idx14: |
| 335 %res14 = insertelement <16 x i8> %vec, i8 %elt, i32 14 |
| 336 ret <16 x i8> %res14 |
| 337 idx15: |
| 338 %res15 = insertelement <16 x i8> %vec, i8 %elt, i32 15 |
| 339 ret <16 x i8> %res15 |
| 340 abort: |
| 341 unreachable |
| 342 } |
| 343 |
| 344 define <16 x i8> @insertelement_v16ui8(<16 x i8> %vec, i64 %elt_arg, i32 %idx) { |
| 345 entry: |
| 346 %res = call <16 x i8> @insertelement_v16si8(<16 x i8> %vec, i64 %elt_arg, i32
%idx) |
| 347 ret <16 x i8> %res |
| 348 } |
| 349 |
| 350 define float @extractelement_v4f32(<4 x float> %vec, i32 %idx) { |
| 351 switch i32 %idx, label %abort [ |
| 352 i32 0, label %idx0 |
| 353 i32 1, label %idx1 |
| 354 i32 2, label %idx2 |
| 355 i32 3, label %idx3 |
| 356 ] |
| 357 idx0: |
| 358 %res0 = extractelement <4 x float> %vec, i32 0 |
| 359 ret float %res0 |
| 360 idx1: |
| 361 %res1 = extractelement <4 x float> %vec, i32 1 |
| 362 ret float %res1 |
| 363 idx2: |
| 364 %res2 = extractelement <4 x float> %vec, i32 2 |
| 365 ret float %res2 |
| 366 idx3: |
| 367 %res3 = extractelement <4 x float> %vec, i32 3 |
| 368 ret float %res3 |
| 369 abort: |
| 370 unreachable |
| 371 } |
| 372 |
| 373 define i64 @extractelement_v4i1(<4 x i32> %arg_vec, i32 %idx) { |
| 374 %vec = trunc <4 x i32> %arg_vec to <4 x i1> |
| 375 switch i32 %idx, label %abort [ |
| 376 i32 0, label %idx0 |
| 377 i32 1, label %idx1 |
| 378 i32 2, label %idx2 |
| 379 i32 3, label %idx3 |
| 380 ] |
| 381 idx0: |
| 382 %res0_i1 = extractelement <4 x i1> %vec, i32 0 |
| 383 %res0 = zext i1 %res0_i1 to i64 |
| 384 ret i64 %res0 |
| 385 idx1: |
| 386 %res1_i1 = extractelement <4 x i1> %vec, i32 1 |
| 387 %res1 = zext i1 %res1_i1 to i64 |
| 388 ret i64 %res1 |
| 389 idx2: |
| 390 %res2_i1 = extractelement <4 x i1> %vec, i32 2 |
| 391 %res2 = zext i1 %res2_i1 to i64 |
| 392 ret i64 %res2 |
| 393 idx3: |
| 394 %res3_i1 = extractelement <4 x i1> %vec, i32 3 |
| 395 %res3 = zext i1 %res3_i1 to i64 |
| 396 ret i64 %res3 |
| 397 abort: |
| 398 unreachable |
| 399 } |
| 400 |
| 401 define i64 @extractelement_v8i1(<8 x i16> %arg_vec, i32 %idx) { |
| 402 %vec = trunc <8 x i16> %arg_vec to <8 x i1> |
| 403 switch i32 %idx, label %abort [ |
| 404 i32 0, label %idx0 |
| 405 i32 1, label %idx1 |
| 406 i32 2, label %idx2 |
| 407 i32 3, label %idx3 |
| 408 i32 4, label %idx4 |
| 409 i32 5, label %idx5 |
| 410 i32 6, label %idx6 |
| 411 i32 7, label %idx7 |
| 412 ] |
| 413 idx0: |
| 414 %res0_i1 = extractelement <8 x i1> %vec, i32 0 |
| 415 %res0 = zext i1 %res0_i1 to i64 |
| 416 ret i64 %res0 |
| 417 idx1: |
| 418 %res1_i1 = extractelement <8 x i1> %vec, i32 1 |
| 419 %res1 = zext i1 %res1_i1 to i64 |
| 420 ret i64 %res1 |
| 421 idx2: |
| 422 %res2_i1 = extractelement <8 x i1> %vec, i32 2 |
| 423 %res2 = zext i1 %res2_i1 to i64 |
| 424 ret i64 %res2 |
| 425 idx3: |
| 426 %res3_i1 = extractelement <8 x i1> %vec, i32 3 |
| 427 %res3 = zext i1 %res3_i1 to i64 |
| 428 ret i64 %res3 |
| 429 idx4: |
| 430 %res4_i1 = extractelement <8 x i1> %vec, i32 4 |
| 431 %res4 = zext i1 %res4_i1 to i64 |
| 432 ret i64 %res4 |
| 433 idx5: |
| 434 %res5_i1 = extractelement <8 x i1> %vec, i32 5 |
| 435 %res5 = zext i1 %res5_i1 to i64 |
| 436 ret i64 %res5 |
| 437 idx6: |
| 438 %res6_i1 = extractelement <8 x i1> %vec, i32 6 |
| 439 %res6 = zext i1 %res6_i1 to i64 |
| 440 ret i64 %res6 |
| 441 idx7: |
| 442 %res7_i1 = extractelement <8 x i1> %vec, i32 7 |
| 443 %res7 = zext i1 %res7_i1 to i64 |
| 444 ret i64 %res7 |
| 445 abort: |
| 446 unreachable |
| 447 } |
| 448 |
| 449 define i64 @extractelement_v16i1(<16 x i8> %arg_vec, i32 %idx) { |
| 450 %vec = trunc <16 x i8> %arg_vec to <16 x i1> |
| 451 switch i32 %idx, label %abort [ |
| 452 i32 0, label %idx0 |
| 453 i32 1, label %idx1 |
| 454 i32 2, label %idx2 |
| 455 i32 3, label %idx3 |
| 456 i32 4, label %idx4 |
| 457 i32 5, label %idx5 |
| 458 i32 6, label %idx6 |
| 459 i32 7, label %idx7 |
| 460 i32 8, label %idx8 |
| 461 i32 9, label %idx9 |
| 462 i32 10, label %idx10 |
| 463 i32 11, label %idx11 |
| 464 i32 12, label %idx12 |
| 465 i32 13, label %idx13 |
| 466 i32 14, label %idx14 |
| 467 i32 15, label %idx15 |
| 468 ] |
| 469 idx0: |
| 470 %res0_i1 = extractelement <16 x i1> %vec, i32 0 |
| 471 %res0 = zext i1 %res0_i1 to i64 |
| 472 ret i64 %res0 |
| 473 idx1: |
| 474 %res1_i1 = extractelement <16 x i1> %vec, i32 1 |
| 475 %res1 = zext i1 %res1_i1 to i64 |
| 476 ret i64 %res1 |
| 477 idx2: |
| 478 %res2_i1 = extractelement <16 x i1> %vec, i32 2 |
| 479 %res2 = zext i1 %res2_i1 to i64 |
| 480 ret i64 %res2 |
| 481 idx3: |
| 482 %res3_i1 = extractelement <16 x i1> %vec, i32 3 |
| 483 %res3 = zext i1 %res3_i1 to i64 |
| 484 ret i64 %res3 |
| 485 idx4: |
| 486 %res4_i1 = extractelement <16 x i1> %vec, i32 4 |
| 487 %res4 = zext i1 %res4_i1 to i64 |
| 488 ret i64 %res4 |
| 489 idx5: |
| 490 %res5_i1 = extractelement <16 x i1> %vec, i32 5 |
| 491 %res5 = zext i1 %res5_i1 to i64 |
| 492 ret i64 %res5 |
| 493 idx6: |
| 494 %res6_i1 = extractelement <16 x i1> %vec, i32 6 |
| 495 %res6 = zext i1 %res6_i1 to i64 |
| 496 ret i64 %res6 |
| 497 idx7: |
| 498 %res7_i1 = extractelement <16 x i1> %vec, i32 7 |
| 499 %res7 = zext i1 %res7_i1 to i64 |
| 500 ret i64 %res7 |
| 501 idx8: |
| 502 %res8_i1 = extractelement <16 x i1> %vec, i32 8 |
| 503 %res8 = zext i1 %res8_i1 to i64 |
| 504 ret i64 %res8 |
| 505 idx9: |
| 506 %res9_i1 = extractelement <16 x i1> %vec, i32 9 |
| 507 %res9 = zext i1 %res9_i1 to i64 |
| 508 ret i64 %res9 |
| 509 idx10: |
| 510 %res10_i1 = extractelement <16 x i1> %vec, i32 10 |
| 511 %res10 = zext i1 %res10_i1 to i64 |
| 512 ret i64 %res10 |
| 513 idx11: |
| 514 %res11_i1 = extractelement <16 x i1> %vec, i32 11 |
| 515 %res11 = zext i1 %res11_i1 to i64 |
| 516 ret i64 %res11 |
| 517 idx12: |
| 518 %res12_i1 = extractelement <16 x i1> %vec, i32 12 |
| 519 %res12 = zext i1 %res12_i1 to i64 |
| 520 ret i64 %res12 |
| 521 idx13: |
| 522 %res13_i1 = extractelement <16 x i1> %vec, i32 13 |
| 523 %res13 = zext i1 %res13_i1 to i64 |
| 524 ret i64 %res13 |
| 525 idx14: |
| 526 %res14_i1 = extractelement <16 x i1> %vec, i32 14 |
| 527 %res14 = zext i1 %res14_i1 to i64 |
| 528 ret i64 %res14 |
| 529 idx15: |
| 530 %res15_i1 = extractelement <16 x i1> %vec, i32 15 |
| 531 %res15 = zext i1 %res15_i1 to i64 |
| 532 ret i64 %res15 |
| 533 abort: |
| 534 unreachable |
| 535 } |
| 536 |
| 537 define i64 @extractelement_v4si32(<4 x i32> %vec, i32 %idx) { |
| 538 entry: |
| 539 switch i32 %idx, label %abort [ |
| 540 i32 0, label %idx0 |
| 541 i32 1, label %idx1 |
| 542 i32 2, label %idx2 |
| 543 i32 3, label %idx3 |
| 544 ] |
| 545 idx0: |
| 546 %res0_i32 = extractelement <4 x i32> %vec, i32 0 |
| 547 %res0 = zext i32 %res0_i32 to i64 |
| 548 ret i64 %res0 |
| 549 idx1: |
| 550 %res1_i32 = extractelement <4 x i32> %vec, i32 1 |
| 551 %res1 = zext i32 %res1_i32 to i64 |
| 552 ret i64 %res1 |
| 553 idx2: |
| 554 %res2_i32 = extractelement <4 x i32> %vec, i32 2 |
| 555 %res2 = zext i32 %res2_i32 to i64 |
| 556 ret i64 %res2 |
| 557 idx3: |
| 558 %res3_i32 = extractelement <4 x i32> %vec, i32 3 |
| 559 %res3 = zext i32 %res3_i32 to i64 |
| 560 ret i64 %res3 |
| 561 abort: |
| 562 unreachable |
| 563 } |
| 564 |
| 565 define i64 @extractelement_v4ui32(<4 x i32> %vec, i32 %idx) { |
| 566 entry: |
| 567 %res = call i64 @extractelement_v4si32(<4 x i32> %vec, i32 %idx) |
| 568 ret i64 %res |
| 569 } |
| 570 |
| 571 define i64 @extractelement_v8si16(<8 x i16> %vec, i32 %idx) { |
| 572 entry: |
| 573 switch i32 %idx, label %abort [ |
| 574 i32 0, label %idx0 |
| 575 i32 1, label %idx1 |
| 576 i32 2, label %idx2 |
| 577 i32 3, label %idx3 |
| 578 i32 4, label %idx4 |
| 579 i32 5, label %idx5 |
| 580 i32 6, label %idx6 |
| 581 i32 7, label %idx7 |
| 582 ] |
| 583 idx0: |
| 584 %res0_i16 = extractelement <8 x i16> %vec, i32 0 |
| 585 %res0 = zext i16 %res0_i16 to i64 |
| 586 ret i64 %res0 |
| 587 idx1: |
| 588 %res1_i16 = extractelement <8 x i16> %vec, i32 1 |
| 589 %res1 = zext i16 %res1_i16 to i64 |
| 590 ret i64 %res1 |
| 591 idx2: |
| 592 %res2_i16 = extractelement <8 x i16> %vec, i32 2 |
| 593 %res2 = zext i16 %res2_i16 to i64 |
| 594 ret i64 %res2 |
| 595 idx3: |
| 596 %res3_i16 = extractelement <8 x i16> %vec, i32 3 |
| 597 %res3 = zext i16 %res3_i16 to i64 |
| 598 ret i64 %res3 |
| 599 idx4: |
| 600 %res4_i16 = extractelement <8 x i16> %vec, i32 4 |
| 601 %res4 = zext i16 %res4_i16 to i64 |
| 602 ret i64 %res4 |
| 603 idx5: |
| 604 %res5_i16 = extractelement <8 x i16> %vec, i32 5 |
| 605 %res5 = zext i16 %res5_i16 to i64 |
| 606 ret i64 %res5 |
| 607 idx6: |
| 608 %res6_i16 = extractelement <8 x i16> %vec, i32 6 |
| 609 %res6 = zext i16 %res6_i16 to i64 |
| 610 ret i64 %res6 |
| 611 idx7: |
| 612 %res7_i16 = extractelement <8 x i16> %vec, i32 7 |
| 613 %res7 = zext i16 %res7_i16 to i64 |
| 614 ret i64 %res7 |
| 615 abort: |
| 616 unreachable |
| 617 } |
| 618 |
| 619 define i64 @extractelement_v8ui16(<8 x i16> %vec, i32 %idx) { |
| 620 entry: |
| 621 %res = call i64 @extractelement_v8si16(<8 x i16> %vec, i32 %idx) |
| 622 ret i64 %res |
| 623 } |
| 624 |
| 625 define i64 @extractelement_v16si8(<16 x i8> %vec, i32 %idx) { |
| 626 entry: |
| 627 switch i32 %idx, label %abort [ |
| 628 i32 0, label %idx0 |
| 629 i32 1, label %idx1 |
| 630 i32 2, label %idx2 |
| 631 i32 3, label %idx3 |
| 632 i32 4, label %idx4 |
| 633 i32 5, label %idx5 |
| 634 i32 6, label %idx6 |
| 635 i32 7, label %idx7 |
| 636 i32 8, label %idx8 |
| 637 i32 9, label %idx9 |
| 638 i32 10, label %idx10 |
| 639 i32 11, label %idx11 |
| 640 i32 12, label %idx12 |
| 641 i32 13, label %idx13 |
| 642 i32 14, label %idx14 |
| 643 i32 15, label %idx15 |
| 644 ] |
| 645 idx0: |
| 646 %res0_i8 = extractelement <16 x i8> %vec, i32 0 |
| 647 %res0 = zext i8 %res0_i8 to i64 |
| 648 ret i64 %res0 |
| 649 idx1: |
| 650 %res1_i8 = extractelement <16 x i8> %vec, i32 1 |
| 651 %res1 = zext i8 %res1_i8 to i64 |
| 652 ret i64 %res1 |
| 653 idx2: |
| 654 %res2_i8 = extractelement <16 x i8> %vec, i32 2 |
| 655 %res2 = zext i8 %res2_i8 to i64 |
| 656 ret i64 %res2 |
| 657 idx3: |
| 658 %res3_i8 = extractelement <16 x i8> %vec, i32 3 |
| 659 %res3 = zext i8 %res3_i8 to i64 |
| 660 ret i64 %res3 |
| 661 idx4: |
| 662 %res4_i8 = extractelement <16 x i8> %vec, i32 4 |
| 663 %res4 = zext i8 %res4_i8 to i64 |
| 664 ret i64 %res4 |
| 665 idx5: |
| 666 %res5_i8 = extractelement <16 x i8> %vec, i32 5 |
| 667 %res5 = zext i8 %res5_i8 to i64 |
| 668 ret i64 %res5 |
| 669 idx6: |
| 670 %res6_i8 = extractelement <16 x i8> %vec, i32 6 |
| 671 %res6 = zext i8 %res6_i8 to i64 |
| 672 ret i64 %res6 |
| 673 idx7: |
| 674 %res7_i8 = extractelement <16 x i8> %vec, i32 7 |
| 675 %res7 = zext i8 %res7_i8 to i64 |
| 676 ret i64 %res7 |
| 677 idx8: |
| 678 %res8_i8 = extractelement <16 x i8> %vec, i32 8 |
| 679 %res8 = zext i8 %res8_i8 to i64 |
| 680 ret i64 %res8 |
| 681 idx9: |
| 682 %res9_i8 = extractelement <16 x i8> %vec, i32 9 |
| 683 %res9 = zext i8 %res9_i8 to i64 |
| 684 ret i64 %res9 |
| 685 idx10: |
| 686 %res10_i8 = extractelement <16 x i8> %vec, i32 10 |
| 687 %res10 = zext i8 %res10_i8 to i64 |
| 688 ret i64 %res10 |
| 689 idx11: |
| 690 %res11_i8 = extractelement <16 x i8> %vec, i32 11 |
| 691 %res11 = zext i8 %res11_i8 to i64 |
| 692 ret i64 %res11 |
| 693 idx12: |
| 694 %res12_i8 = extractelement <16 x i8> %vec, i32 12 |
| 695 %res12 = zext i8 %res12_i8 to i64 |
| 696 ret i64 %res12 |
| 697 idx13: |
| 698 %res13_i8 = extractelement <16 x i8> %vec, i32 13 |
| 699 %res13 = zext i8 %res13_i8 to i64 |
| 700 ret i64 %res13 |
| 701 idx14: |
| 702 %res14_i8 = extractelement <16 x i8> %vec, i32 14 |
| 703 %res14 = zext i8 %res14_i8 to i64 |
| 704 ret i64 %res14 |
| 705 idx15: |
| 706 %res15_i8 = extractelement <16 x i8> %vec, i32 15 |
| 707 %res15 = zext i8 %res15_i8 to i64 |
| 708 ret i64 %res15 |
| 709 abort: |
| 710 unreachable |
| 711 } |
| 712 |
| 713 define i64 @extractelement_v16ui8(<16 x i8> %vec, i32 %idx) { |
| 714 entry: |
| 715 %res = call i64 @extractelement_v16si8(<16 x i8> %vec, i32 %idx) |
| 716 ret i64 %res |
| 717 } |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 401523003:
Lower insertelement and extractelement. (Closed)
Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master