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Issue 391073: Changes to Intel shift functions... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 11 years, 1 month ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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1084 EMIT(0xD1); 1084 EMIT(0xD1);
1085 EMIT(0xF8 | dst.code()); 1085 EMIT(0xF8 | dst.code());
1086 } else { 1086 } else {
1087 EMIT(0xC1); 1087 EMIT(0xC1);
1088 EMIT(0xF8 | dst.code()); 1088 EMIT(0xF8 | dst.code());
1089 EMIT(imm8); 1089 EMIT(imm8);
1090 } 1090 }
1091 } 1091 }
1092 1092
1093 1093
1094 void Assembler::sar(Register dst) { 1094 void Assembler::sar_cl(Register dst) {
1095 EnsureSpace ensure_space(this); 1095 EnsureSpace ensure_space(this);
1096 last_pc_ = pc_; 1096 last_pc_ = pc_;
1097 EMIT(0xD3); 1097 EMIT(0xD3);
1098 EMIT(0xF8 | dst.code()); 1098 EMIT(0xF8 | dst.code());
1099 } 1099 }
1100 1100
1101 1101
1102 void Assembler::sbb(Register dst, const Operand& src) { 1102 void Assembler::sbb(Register dst, const Operand& src) {
1103 EnsureSpace ensure_space(this); 1103 EnsureSpace ensure_space(this);
1104 last_pc_ = pc_; 1104 last_pc_ = pc_;
(...skipping 19 matching lines...) Expand all
1124 EMIT(0xD1); 1124 EMIT(0xD1);
1125 EMIT(0xE0 | dst.code()); 1125 EMIT(0xE0 | dst.code());
1126 } else { 1126 } else {
1127 EMIT(0xC1); 1127 EMIT(0xC1);
1128 EMIT(0xE0 | dst.code()); 1128 EMIT(0xE0 | dst.code());
1129 EMIT(imm8); 1129 EMIT(imm8);
1130 } 1130 }
1131 } 1131 }
1132 1132
1133 1133
1134 void Assembler::shl(Register dst) { 1134 void Assembler::shl_cl(Register dst) {
1135 EnsureSpace ensure_space(this); 1135 EnsureSpace ensure_space(this);
1136 last_pc_ = pc_; 1136 last_pc_ = pc_;
1137 EMIT(0xD3); 1137 EMIT(0xD3);
1138 EMIT(0xE0 | dst.code()); 1138 EMIT(0xE0 | dst.code());
1139 } 1139 }
1140 1140
1141 1141
1142 void Assembler::shrd(Register dst, const Operand& src) { 1142 void Assembler::shrd(Register dst, const Operand& src) {
1143 EnsureSpace ensure_space(this); 1143 EnsureSpace ensure_space(this);
1144 last_pc_ = pc_; 1144 last_pc_ = pc_;
1145 EMIT(0x0F); 1145 EMIT(0x0F);
1146 EMIT(0xAD); 1146 EMIT(0xAD);
1147 emit_operand(dst, src); 1147 emit_operand(dst, src);
1148 } 1148 }
1149 1149
1150 1150
1151 void Assembler::shr(Register dst, uint8_t imm8) { 1151 void Assembler::shr(Register dst, uint8_t imm8) {
1152 EnsureSpace ensure_space(this); 1152 EnsureSpace ensure_space(this);
1153 last_pc_ = pc_; 1153 last_pc_ = pc_;
1154 ASSERT(is_uint5(imm8)); // illegal shift count 1154 ASSERT(is_uint5(imm8)); // illegal shift count
1155 EMIT(0xC1); 1155 if (imm8 == 1) {
1156 EMIT(0xE8 | dst.code()); 1156 EMIT(0xD1);
1157 EMIT(imm8); 1157 EMIT(0xE8 | dst.code());
1158 } else {
1159 EMIT(0xC1);
1160 EMIT(0xE8 | dst.code());
1161 EMIT(imm8);
1162 }
1158 } 1163 }
1159 1164
1160 1165
1161 void Assembler::shr(Register dst) { 1166 void Assembler::shr_cl(Register dst) {
1162 EnsureSpace ensure_space(this); 1167 EnsureSpace ensure_space(this);
1163 last_pc_ = pc_; 1168 last_pc_ = pc_;
1164 EMIT(0xD3); 1169 EMIT(0xD3);
1165 EMIT(0xE8 | dst.code()); 1170 EMIT(0xE8 | dst.code());
1166 } 1171 }
1167 1172
1168 1173
1169 void Assembler::shr_cl(Register dst) {
1170 EnsureSpace ensure_space(this);
1171 last_pc_ = pc_;
1172 EMIT(0xD1);
Lasse Reichstein 2009/11/17 08:30:36 So this one was actually wrong before. Was it used
Søren Thygesen Gjesse 2009/11/17 08:35:10 It was wrong but not used.
1173 EMIT(0xE8 | dst.code());
1174 }
1175
1176
1177 void Assembler::subb(const Operand& op, int8_t imm8) { 1174 void Assembler::subb(const Operand& op, int8_t imm8) {
1178 EnsureSpace ensure_space(this); 1175 EnsureSpace ensure_space(this);
1179 last_pc_ = pc_; 1176 last_pc_ = pc_;
1180 if (op.is_reg(eax)) { 1177 if (op.is_reg(eax)) {
1181 EMIT(0x2c); 1178 EMIT(0x2c);
1182 } else { 1179 } else {
1183 EMIT(0x80); 1180 EMIT(0x80);
1184 emit_operand(ebp, op); // ebp == 5 1181 emit_operand(ebp, op); // ebp == 5
1185 } 1182 }
1186 EMIT(imm8); 1183 EMIT(imm8);
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2287 push_insn[1] = 13; // Skip over coverage insns. 2284 push_insn[1] = 13; // Skip over coverage insns.
2288 if (coverage_log != NULL) { 2285 if (coverage_log != NULL) {
2289 fprintf(coverage_log, "%s\n", file_line); 2286 fprintf(coverage_log, "%s\n", file_line);
2290 fflush(coverage_log); 2287 fflush(coverage_log);
2291 } 2288 }
2292 } 2289 }
2293 2290
2294 #endif 2291 #endif
2295 2292
2296 } } // namespace v8::internal 2293 } } // namespace v8::internal
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