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Side by Side Diff: runtime/vm/assembler_ia32.cc

Issue 387733002: Specialize mint shift code on ia32 for a constant shift amount. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 5 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_IA32) 6 #if defined(TARGET_ARCH_IA32)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/code_generator.h" 9 #include "vm/code_generator.h"
10 #include "vm/cpu.h" 10 #include "vm/cpu.h"
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1731 1731
1732 1732
1733 void Assembler::shld(Register dst, Register src) { 1733 void Assembler::shld(Register dst, Register src) {
1734 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1734 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1735 EmitUint8(0x0F); 1735 EmitUint8(0x0F);
1736 EmitUint8(0xA5); 1736 EmitUint8(0xA5);
1737 EmitRegisterOperand(src, dst); 1737 EmitRegisterOperand(src, dst);
1738 } 1738 }
1739 1739
1740 1740
1741 void Assembler::shld(Register dst, Register src, const Immediate& imm) {
1742 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1743 ASSERT(imm.is_int8());
1744 EmitUint8(0x0F);
1745 EmitUint8(0xA4);
1746 EmitRegisterOperand(src, dst);
1747 EmitUint8(imm.value() & 0xFF);
1748 }
1749
1750
1741 void Assembler::shld(const Address& operand, Register src) { 1751 void Assembler::shld(const Address& operand, Register src) {
1742 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1752 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1743 EmitUint8(0x0F); 1753 EmitUint8(0x0F);
1744 EmitUint8(0xA5); 1754 EmitUint8(0xA5);
1745 EmitOperand(src, Operand(operand)); 1755 EmitOperand(src, Operand(operand));
1746 } 1756 }
1747 1757
1758
1748 void Assembler::shrd(Register dst, Register src) { 1759 void Assembler::shrd(Register dst, Register src) {
1749 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1760 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1750 EmitUint8(0x0F); 1761 EmitUint8(0x0F);
1751 EmitUint8(0xAD); 1762 EmitUint8(0xAD);
1752 EmitRegisterOperand(src, dst); 1763 EmitRegisterOperand(src, dst);
1753 } 1764 }
1754 1765
1755 1766
1767 void Assembler::shrd(Register dst, Register src, const Immediate& imm) {
1768 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1769 ASSERT(imm.is_int8());
1770 EmitUint8(0x0F);
1771 EmitUint8(0xAC);
1772 EmitRegisterOperand(src, dst);
1773 EmitUint8(imm.value() & 0xFF);
1774 }
1775
1776
1756 void Assembler::shrd(const Address& dst, Register src) { 1777 void Assembler::shrd(const Address& dst, Register src) {
1757 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1778 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1758 EmitUint8(0x0F); 1779 EmitUint8(0x0F);
1759 EmitUint8(0xAD); 1780 EmitUint8(0xAD);
1760 EmitOperand(src, Operand(dst)); 1781 EmitOperand(src, Operand(dst));
1761 } 1782 }
1762 1783
1763 1784
1764 void Assembler::negl(Register reg) { 1785 void Assembler::negl(Register reg) {
1765 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1786 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
(...skipping 953 matching lines...) Expand 10 before | Expand all | Expand 10 after
2719 2740
2720 const char* Assembler::FpuRegisterName(FpuRegister reg) { 2741 const char* Assembler::FpuRegisterName(FpuRegister reg) {
2721 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters)); 2742 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
2722 return xmm_reg_names[reg]; 2743 return xmm_reg_names[reg];
2723 } 2744 }
2724 2745
2725 2746
2726 } // namespace dart 2747 } // namespace dart
2727 2748
2728 #endif // defined TARGET_ARCH_IA32 2749 #endif // defined TARGET_ARCH_IA32
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