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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// | 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file implements the TargetLoweringX8632 class, which | 10 // This file implements the TargetLoweringX8632 class, which |
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2749 Variable *Dest = NULL; | 2749 Variable *Dest = NULL; |
2750 InstCall *Call = makeHelperCall("ice_unreachable", Dest, MaxSrcs); | 2750 InstCall *Call = makeHelperCall("ice_unreachable", Dest, MaxSrcs); |
2751 lowerCall(Call); | 2751 lowerCall(Call); |
2752 } | 2752 } |
2753 | 2753 |
2754 // Helper for legalize() to emit the right code to lower an operand to a | 2754 // Helper for legalize() to emit the right code to lower an operand to a |
2755 // register of the appropriate type. | 2755 // register of the appropriate type. |
2756 Variable *TargetX8632::copyToReg(Operand *Src, int32_t RegNum) { | 2756 Variable *TargetX8632::copyToReg(Operand *Src, int32_t RegNum) { |
2757 Type Ty = Src->getType(); | 2757 Type Ty = Src->getType(); |
2758 Variable *Reg = makeReg(Ty, RegNum); | 2758 Variable *Reg = makeReg(Ty, RegNum); |
2759 if (isVectorType(Src->getType())) { | 2759 if (isVectorType(Ty)) { |
2760 _movp(Reg, Src); | 2760 _movp(Reg, Src); |
2761 } else { | 2761 } else { |
2762 _mov(Reg, Src); | 2762 _mov(Reg, Src); |
2763 } | 2763 } |
2764 return Reg; | 2764 return Reg; |
2765 } | 2765 } |
2766 | 2766 |
2767 Operand *TargetX8632::legalize(Operand *From, LegalMask Allowed, | 2767 Operand *TargetX8632::legalize(Operand *From, LegalMask Allowed, |
2768 bool AllowOverlap, int32_t RegNum) { | 2768 bool AllowOverlap, int32_t RegNum) { |
2769 // Assert that a physical register is allowed. To date, all calls | 2769 // Assert that a physical register is allowed. To date, all calls |
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2820 Variable *Reg = makeReg(From->getType(), RegNum); | 2820 Variable *Reg = makeReg(From->getType(), RegNum); |
2821 // Insert a FakeDef, since otherwise the live range of Reg might | 2821 // Insert a FakeDef, since otherwise the live range of Reg might |
2822 // be overestimated. | 2822 // be overestimated. |
2823 Context.insert(InstFakeDef::create(Func, Reg)); | 2823 Context.insert(InstFakeDef::create(Func, Reg)); |
2824 _pxor(Reg, Reg); | 2824 _pxor(Reg, Reg); |
2825 return Reg; | 2825 return Reg; |
2826 } else { | 2826 } else { |
2827 From = Ctx->getConstantZero(From->getType()); | 2827 From = Ctx->getConstantZero(From->getType()); |
2828 } | 2828 } |
2829 } | 2829 } |
| 2830 // There should be no constants of vector type (other than undef). |
| 2831 assert(!isVectorType(From->getType())); |
2830 bool NeedsReg = false; | 2832 bool NeedsReg = false; |
2831 if (!(Allowed & Legal_Imm)) | 2833 if (!(Allowed & Legal_Imm)) |
2832 // Immediate specifically not allowed | 2834 // Immediate specifically not allowed |
2833 NeedsReg = true; | 2835 NeedsReg = true; |
2834 // TODO(stichnot): LEAHACK: remove Legal_Reloc once a proper | 2836 // TODO(stichnot): LEAHACK: remove Legal_Reloc once a proper |
2835 // emitter is used. | 2837 // emitter is used. |
2836 if (!(Allowed & Legal_Reloc) && llvm::isa<ConstantRelocatable>(From)) | 2838 if (!(Allowed & Legal_Reloc) && llvm::isa<ConstantRelocatable>(From)) |
2837 // Relocatable specifically not allowed | 2839 // Relocatable specifically not allowed |
2838 NeedsReg = true; | 2840 NeedsReg = true; |
2839 if (!(Allowed & Legal_Mem) && | 2841 if (!(Allowed & Legal_Mem) && |
2840 (From->getType() == IceType_f32 || From->getType() == IceType_f64)) | 2842 (From->getType() == IceType_f32 || From->getType() == IceType_f64)) |
2841 // On x86, FP constants are lowered to mem operands. | 2843 // On x86, FP constants are lowered to mem operands. |
2842 NeedsReg = true; | 2844 NeedsReg = true; |
2843 if (NeedsReg) { | 2845 if (NeedsReg) { |
2844 From = copyToReg(From, RegNum); | 2846 From = copyToReg(From, RegNum); |
2845 } | 2847 } |
2846 return From; | 2848 return From; |
2847 } | 2849 } |
2848 if (Variable *Var = llvm::dyn_cast<Variable>(From)) { | 2850 if (Variable *Var = llvm::dyn_cast<Variable>(From)) { |
| 2851 // Check if the variable is guaranteed a physical register. This |
| 2852 // can happen either when the variable is pre-colored or when it is |
| 2853 // assigned infinite weight. |
| 2854 bool MustHaveRegister = |
| 2855 (Var->hasReg() || Var->getWeight() == RegWeight::Inf); |
2849 // We need a new physical register for the operand if: | 2856 // We need a new physical register for the operand if: |
2850 // Mem is not allowed and Var isn't guaranteed a physical | 2857 // Mem is not allowed and Var isn't guaranteed a physical |
2851 // register, or | 2858 // register, or |
2852 // RegNum is required and Var->getRegNum() doesn't match. | 2859 // RegNum is required and Var->getRegNum() doesn't match. |
2853 bool WillHaveRegister = | 2860 if ((!(Allowed & Legal_Mem) && !MustHaveRegister) || |
2854 (Var->hasReg() || Var->getWeight() == RegWeight::Inf); | |
2855 if ((!(Allowed & Legal_Mem) && !WillHaveRegister) || | |
2856 (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) { | 2861 (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) { |
2857 Variable *Reg = copyToReg(From, RegNum); | 2862 Variable *Reg = copyToReg(From, RegNum); |
2858 if (RegNum == Variable::NoRegister) { | 2863 if (RegNum == Variable::NoRegister) { |
2859 Reg->setPreferredRegister(Var, AllowOverlap); | 2864 Reg->setPreferredRegister(Var, AllowOverlap); |
2860 } | 2865 } |
2861 From = Reg; | 2866 From = Reg; |
2862 } | 2867 } |
2863 return From; | 2868 return From; |
2864 } | 2869 } |
2865 llvm_unreachable("Unhandled operand kind in legalize()"); | 2870 llvm_unreachable("Unhandled operand kind in legalize()"); |
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3070 for (SizeT i = 0; i < Size; ++i) { | 3075 for (SizeT i = 0; i < Size; ++i) { |
3071 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n"; | 3076 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n"; |
3072 } | 3077 } |
3073 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; | 3078 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; |
3074 } | 3079 } |
3075 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName | 3080 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName |
3076 << "\n"; | 3081 << "\n"; |
3077 } | 3082 } |
3078 | 3083 |
3079 } // end of namespace Ice | 3084 } // end of namespace Ice |
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