Various improvements related to legalization code.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 2558 matching lines @@
   Variable *Dest = NULL;
   InstCall *Call = makeHelperCall("ice_unreachable", Dest, MaxSrcs);
   lowerCall(Call);
 }
 
 // Helper for legalize() to emit the right code to lower an operand to a
 // register of the appropriate type.
 Variable *TargetX8632::copyToReg(Operand *Src, int32_t RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
-  if (isVectorType(Src->getType())) {
+  if (isVectorType(Ty)) {
     _movp(Reg, Src);
   } else {
     _mov(Reg, Src);
   }
   return Reg;
 }
 
 Operand *TargetX8632::legalize(Operand *From, LegalMask Allowed,
                                bool AllowOverlap, int32_t RegNum) {
   // Assert that a physical register is allowed.  To date, all calls
@@ skipping 50 matching lines @@
         Variable *Reg = makeReg(From->getType(), RegNum);
         // Insert a FakeDef, since otherwise the live range of Reg might
         // be overestimated.
         Context.insert(InstFakeDef::create(Func, Reg));
         _pxor(Reg, Reg);
         return Reg;
       } else {
         From = Ctx->getConstantZero(From->getType());
       }
     }
+    // There should be no constants of vector type (other than undef).
+    assert(!isVectorType(From->getType()));
     bool NeedsReg = false;
     if (!(Allowed & Legal_Imm))
       // Immediate specifically not allowed
       NeedsReg = true;
     // TODO(stichnot): LEAHACK: remove Legal_Reloc once a proper
     // emitter is used.
     if (!(Allowed & Legal_Reloc) && llvm::isa<ConstantRelocatable>(From))
       // Relocatable specifically not allowed
       NeedsReg = true;
     if (!(Allowed & Legal_Mem) &&
         (From->getType() == IceType_f32 || From->getType() == IceType_f64))
       // On x86, FP constants are lowered to mem operands.
       NeedsReg = true;
     if (NeedsReg) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   if (Variable *Var = llvm::dyn_cast<Variable>(From)) {
     // We need a new physical register for the operand if:
     //   Mem is not allowed and Var isn't guaranteed a physical
     //   register, or
     //   RegNum is required and Var->getRegNum() doesn't match.
-    bool WillHaveRegister =
+    bool AlreadyInRegister =

[Jim Stichnoth, 2014/07/14 19:44:17]

To me, WillHaveRegister captures the situation where no specific physical
register has been assigned/precolored, but it has been assigned infinite weight
so it is guaranteed to have a physical register in the future.

AlreadyInRegister only captures the precolored variable situation, IMO.

I would either find a more perfect name :) , or perhaps better yet just add this
clarification to the comment.

[wala, 2014/07/14 20:40:03]

How about MustHaveRegister?

For me, WillHaveRegister suggests the meaning that the variable will be assigned
to a register (and it's not necessarily precolored or infinite weight), which of
course can't be computed at this stage.

         (Var->hasReg() || Var->getWeight() == RegWeight::Inf);
-    if ((!(Allowed & Legal_Mem) && !WillHaveRegister) ||
+    if ((!(Allowed & Legal_Mem) && !AlreadyInRegister) ||
         (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
       Variable *Reg = copyToReg(From, RegNum);
       if (RegNum == Variable::NoRegister) {
         Reg->setPreferredRegister(Var, AllowOverlap);
       }
       From = Reg;
     }
     return From;
   }
   llvm_unreachable("Unhandled operand kind in legalize()");
@@ skipping 204 matching lines @@
     for (SizeT i = 0; i < Size; ++i) {
       Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n";
     }
     Str << "\t.size\t" << MangledName << ", " << Size << "\n";
   }
   Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName
       << "\n";
 }
 
 } // end of namespace Ice