Lower casting operations that involve vector types.

tests_lit/llvm2ice_tests/vector-cast.ll

+; This file tests casting / conversion operations that apply to vector types.
+
+; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
+; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s
+; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
+; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
+; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
+; RUN:                           | FileCheck --check-prefix=DUMP %s
+
+; bitcast operations
+
+define <16 x i8> @test_bitcast_v16i8_to_v16i8(<16 x i8> %arg) {
+entry:
+  %res = bitcast <16 x i8> %arg to <16 x i8>
+  ret <16 x i8> %res
+
+; CHECK-LABEL: test_bitcast_v16i8_to_v16i8:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret

[jvoung (off chromium), 2014/07/15 00:24:11]

Are these the only cases where OPTM1 differs from CHECK?

Just wondering if it could be simplified, by splitting this test, to check the
same thing in both opt levels.

[wala, 2014/07/15 00:41:09]

Yes, the test for bitcast is basically checking that bitcast is lowered to a
no-op in -O2, because -O2 should be smart enough to do this. There is some
additional register / memory shuffling code that makes Om1 output less easy to
test.

I can move the bitcast tests out to a separate file.

[wala, 2014/07/15 22:52:22]

Done.

+}
+
+define <8 x i16> @test_bitcast_v16i8_to_v8i16(<16 x i8> %arg) {
+entry:
+  %res = bitcast <16 x i8> %arg to <8 x i16>
+  ret <8 x i16> %res
+
+; CHECK-LABEL: test_bitcast_v16i8_to_v8i16:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <4 x i32> @test_bitcast_v16i8_to_v4i32(<16 x i8> %arg) {
+entry:
+  %res = bitcast <16 x i8> %arg to <4 x i32>
+  ret <4 x i32> %res
+
+; CHECK-LABEL: test_bitcast_v16i8_to_v4i32:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <4 x float> @test_bitcast_v16i8_to_v4f32(<16 x i8> %arg) {
+entry:
+  %res = bitcast <16 x i8> %arg to <4 x float>
+  ret <4 x float> %res
+
+; CHECK-LABEL: test_bitcast_v16i8_to_v4f32:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <16 x i8> @test_bitcast_v8i16_to_v16i8(<8 x i16> %arg) {
+entry:
+  %res = bitcast <8 x i16> %arg to <16 x i8>
+  ret <16 x i8> %res
+
+; CHECK-LABEL: test_bitcast_v8i16_to_v16i8:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <8 x i16> @test_bitcast_v8i16_to_v8i16(<8 x i16> %arg) {
+entry:
+  %res = bitcast <8 x i16> %arg to <8 x i16>
+  ret <8 x i16> %res
+
+; CHECK-LABEL: test_bitcast_v8i16_to_v8i16:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <4 x i32> @test_bitcast_v8i16_to_v4i32(<8 x i16> %arg) {
+entry:
+  %res = bitcast <8 x i16> %arg to <4 x i32>
+  ret <4 x i32> %res
+
+; CHECK-LABEL: test_bitcast_v8i16_to_v4i32:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <4 x float> @test_bitcast_v8i16_to_v4f32(<8 x i16> %arg) {
+entry:
+  %res = bitcast <8 x i16> %arg to <4 x float>
+  ret <4 x float> %res
+
+; CHECK-LABEL: test_bitcast_v8i16_to_v4f32:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <16 x i8> @test_bitcast_v4i32_to_v16i8(<4 x i32> %arg) {
+entry:
+  %res = bitcast <4 x i32> %arg to <16 x i8>
+  ret <16 x i8> %res
+
+; CHECK-LABEL: test_bitcast_v4i32_to_v16i8:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <8 x i16> @test_bitcast_v4i32_to_v8i16(<4 x i32> %arg) {
+entry:
+  %res = bitcast <4 x i32> %arg to <8 x i16>
+  ret <8 x i16> %res
+
+; CHECK-LABEL: test_bitcast_v4i32_to_v8i16:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <4 x i32> @test_bitcast_v4i32_to_v4i32(<4 x i32> %arg) {
+entry:
+  %res = bitcast <4 x i32> %arg to <4 x i32>
+  ret <4 x i32> %res
+
+; CHECK-LABEL: test_bitcast_v4i32_to_v4i32:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <4 x float> @test_bitcast_v4i32_to_v4f32(<4 x i32> %arg) {
+entry:
+  %res = bitcast <4 x i32> %arg to <4 x float>
+  ret <4 x float> %res
+
+; CHECK-LABEL: test_bitcast_v4i32_to_v4f32:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <16 x i8> @test_bitcast_v4f32_to_v16i8(<4 x float> %arg) {
+entry:
+  %res = bitcast <4 x float> %arg to <16 x i8>
+  ret <16 x i8> %res
+
+; CHECK-LABEL: test_bitcast_v4f32_to_v16i8:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <8 x i16> @test_bitcast_v4f32_to_v8i16(<4 x float> %arg) {
+entry:
+  %res = bitcast <4 x float> %arg to <8 x i16>
+  ret <8 x i16> %res
+
+; CHECK-LABEL: test_bitcast_v4f32_to_v8i16:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <4 x i32> @test_bitcast_v4f32_to_v4i32(<4 x float> %arg) {
+entry:
+  %res = bitcast <4 x float> %arg to <4 x i32>
+  ret <4 x i32> %res
+
+; CHECK-LABEL: test_bitcast_v4f32_to_v4i32:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define <4 x float> @test_bitcast_v4f32_to_v4f32(<4 x float> %arg) {
+entry:
+  %res = bitcast <4 x float> %arg to <4 x float>
+  ret <4 x float> %res
+
+; CHECK-LABEL: test_bitcast_v4f32_to_v4f32:
+; CHECK: .L{{.*}}entry:
+; CHECK-NEXT: ret
+}
+
+define i8 @test_bitcast_v8i1_to_i8(<8 x i1> %arg) {
+entry:
+  %res = bitcast <8 x i1> %arg to i8
+  ret i8 %res
+
+; CHECK-LABEL: test_bitcast_v8i1_to_i8:
+; CHECK: call __bitcast_v8i1_to_i8
+
+; OPTM1-LABEL: test_bitcast_v8i1_to_i8:
+; OPTM1: call __bitcast_v8i1_to_i8
+}
+
+define i16 @test_bitcast_v16i1_to_i16(<16 x i1> %arg) {
+entry:
+  %res = bitcast <16 x i1> %arg to i16
+  ret i16 %res
+
+; CHECK-LABEL: test_bitcast_v16i1_to_i16:
+; CHECK: call __bitcast_v16i1_to_i16
+
+; OPTM1-LABEL: test_bitcast_v16i1_to_i16:
+; OPTM1: call __bitcast_v16i1_to_i16
+}
+
+define <8 x i1> @test_bitcast_i8_to_v8i1(i8 %arg) {
+entry:
+  %res = bitcast i8 %arg to <8 x i1>
+  ret <8 x i1> %res
+
+; CHECK-LABEL: test_bitcast_i8_to_v8i1:
+; CHECK: call __bitcast_i8_to_v8i1
+
+; OPTM1-LABEL: test_bitcast_i8_to_v8i1:
+; OPTM1: call __bitcast_i8_to_v8i1
+}
+
+define <16 x i1> @test_bitcast_i16_to_v16i1(i16 %arg) {
+entry:
+  %res = bitcast i16 %arg to <16 x i1>
+  ret <16 x i1> %res
+
+; CHECK-LABEL: test_bitcast_i16_to_v16i1:
+; CHECK: call __bitcast_i16_to_v16i1
+
+; OPTM1-LABEL: test_bitcast_i16_to_v16i1:
+; OPTM1: call __bitcast_i16_to_v16i1
+}
+
+; sext operations
+
+define <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) {
+entry:
+  %res = sext <16 x i1> %arg to <16 x i8>
+  ret <16 x i8> %res
+
+; CHECK-LABEL: test_sext_v16i1_to_v16i8:
+; CHECK: pxor
+; CHECK: pcmpeqb
+; CHECK: psubb
+; CHECK: pand
+; CHECK: pxor
+; CHECK: pcmpgtb
+
+; OPTM1-LABEL: test_sext_v16i1_to_v16i8:
+; OPTM1: pxor
+; OPTM1: pcmpeqb
+; OPTM1: psubb
+; OPTM1: pand
+; OPTM1: pxor
+; OPTM1: pcmpgtb
+}
+
+define <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) {
+entry:
+  %res = sext <8 x i1> %arg to <8 x i16>
+  ret <8 x i16> %res
+
+; CHECK-LABEL: test_sext_v8i1_to_v8i16:
+; CHECK: psllw {{.*}}, 15
+; CHECK: psraw {{.*}}, 15
+
+; OPTM1-LABEL: test_sext_v8i1_to_v8i16:
+; OPTM1: psllw {{.*}}, 15
+; OPTM1: psraw {{.*}}, 15
+}
+
+define <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) {
+entry:
+  %res = sext <4 x i1> %arg to <4 x i32>
+  ret <4 x i32> %res
+
+; CHECK-LABEL: test_sext_v4i1_to_v4i32:
+; CHECK: pslld {{.*}}, 31
+; CHECK: psrad {{.*}}, 31
+
+; OPTM1-LABEL: test_sext_v4i1_to_v4i32:
+; OPTM1: pslld {{.*}}, 31
+; OPTM1: psrad {{.*}}, 31
+}
+
+; zext operations
+
+define <16 x i8> @test_zext_v16i1_to_v16i8(<16 x i1> %arg) {
+entry:
+  %res = zext <16 x i1> %arg to <16 x i8>
+  ret <16 x i8> %res
+
+; CHECK-LABEL: test_zext_v16i1_to_v16i8:
+; CHECK: pxor
+; CHECK: pcmpeqb
+; CHECK: psubb
+; CHECK: pand
+
+; OPTM1-LABEL: test_zext_v16i1_to_v16i8:
+; OPTM1: pxor
+; OPTM1: pcmpeqb
+; OPTM1: psubb
+; OPTM1: pand
+}
+
+define <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) {
+entry:
+  %res = zext <8 x i1> %arg to <8 x i16>
+  ret <8 x i16> %res
+
+; CHECK-LABEL: test_zext_v8i1_to_v8i16:
+; CHECK: pxor
+; CHECK: pcmpeqw
+; CHECK: psubw
+; CHECK: pand
+
+; OPTM1-LABEL: test_zext_v8i1_to_v8i16:
+; OPTM1: pxor
+; OPTM1: pcmpeqw
+; OPTM1: psubw
+; OPTM1: pand
+}
+
+define <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) {
+entry:
+  %res = zext <4 x i1> %arg to <4 x i32>
+  ret <4 x i32> %res
+
+; CHECK-LABEL: test_zext_v4i1_to_v4i32:
+; CHECK: pxor
+; CHECK: pcmpeqd
+; CHECK: psubd
+; CHECK: pand
+
+; OPTM1-LABEL: test_zext_v4i1_to_v4i32:
+; OPTM1: pxor
+; OPTM1: pcmpeqd
+; OPTM1: psubd
+; OPTM1: pand
+}
+
+; trunc operations
+
+define <16 x i1> @test_trunc_v16i8_to_v16i1(<16 x i8> %arg) {
+entry:
+  %res = trunc <16 x i8> %arg to <16 x i1>
+  ret <16 x i1> %res
+
+; CHECK-LABEL: test_trunc_v16i8_to_v16i1:
+; CHECK: pxor
+; CHECK: pcmpeqb
+; CHECK: psubb
+; CHECK: pand
+
+; OPTM1-LABEL: test_trunc_v16i8_to_v16i1:
+; OPTM1: pxor
+; OPTM1: pcmpeqb
+; OPTM1: psubb
+; OPTM1: pand
+}
+
+define <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) {
+entry:
+  %res = trunc <8 x i16> %arg to <8 x i1>
+  ret <8 x i1> %res
+
+; CHECK-LABEL: test_trunc_v8i16_to_v8i1:
+; CHECK: pxor
+; CHECK: pcmpeqw
+; CHECK: psubw
+; CHECK: pand
+
+; OPTM1-LABEL: test_trunc_v8i16_to_v8i1:
+; OPTM1: pxor
+; OPTM1: pcmpeqw
+; OPTM1: psubw
+; OPTM1: pand
+}
+
+define <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) {
+entry:
+  %res = trunc <4 x i32> %arg to <4 x i1>
+  ret <4 x i1> %res
+
+; CHECK-LABEL: test_trunc_v4i32_to_v4i1:
+; CHECK: pxor
+; CHECK: pcmpeqd
+; CHECK: psubd
+; CHECK: pand
+
+; OPTM1-LABEL: test_trunc_v4i32_to_v4i1:
+; OPTM1: pxor
+; OPTM1: pcmpeqd
+; OPTM1: psubd
+; OPTM1: pand
+}
+
+; fpto[us]i operations
+
+define <4 x i32> @test_fptosi_v4f32_to_v4i32(<4 x float> %arg) {
+entry:
+  %res = fptosi <4 x float> %arg to <4 x i32>
+  ret <4 x i32> %res
+
+; CHECK-LABEL: test_fptosi_v4f32_to_v4i32:
+; CHECK: cvtps2dq
+
+; OPTM1-LABEL: test_fptosi_v4f32_to_v4i32:
+; OPTM1: cvtps2dq
+}
+
+define <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) {
+entry:
+  %res = fptoui <4 x float> %arg to <4 x i32>
+  ret <4 x i32> %res
+
+; CHECK-LABEL: test_fptoui_v4f32_to_v4i32:
+; CHECK: call __fptoui_v4f32
+
+; OPTM1-LABEL: test_fptoui_v4f32_to_v4i32:
+; OPTM1: call __fptoui_v4f32
+}
+
+; [su]itofp operations
+
+define <4 x float> @test_sitofp_v4i32_to_v4f32(<4 x i32> %arg) {
+entry:
+  %res = sitofp <4 x i32> %arg to <4 x float>
+  ret <4 x float> %res
+
+; CHECK-LABEL: test_sitofp_v4i32_to_v4f32:
+; CHECK: cvtdq2ps
+
+; OPTM1-LABEL: test_sitofp_v4i32_to_v4f32:
+; OPTM1: cvtdq2ps
+}
+
+define <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) {
+entry:
+  %res = uitofp <4 x i32> %arg to <4 x float>
+  ret <4 x float> %res
+
+; CHECK-LABEL: test_uitofp_v4i32_to_v4f32:
+; CHECK: call __uitofp_v4i32
+
+; OPTM1-LABEL: test_uitofp_v4i32_to_v4f32:
+; OPTM1: call __uitofp_v4i32
+}
+
+; ERRORS-NOT: ICE translation error
+; DUMP-NOT: SZ