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Side by Side Diff: src/IceTargetLoweringX8632.cpp

Issue 380363002: Subzero: Fix a regalloc bug involving too-aggressive AllowRegisterOverlap. (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Add PrecoloredUnhandled to the output Created 6 years, 5 months ago
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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the TargetLoweringX8632 class, which 10 // This file implements the TargetLoweringX8632 class, which
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2608 (From->getType() == IceType_f32 || From->getType() == IceType_f64)) 2608 (From->getType() == IceType_f32 || From->getType() == IceType_f64))
2609 // On x86, FP constants are lowered to mem operands. 2609 // On x86, FP constants are lowered to mem operands.
2610 NeedsReg = true; 2610 NeedsReg = true;
2611 if (NeedsReg) { 2611 if (NeedsReg) {
2612 From = copyToReg(From, RegNum); 2612 From = copyToReg(From, RegNum);
2613 } 2613 }
2614 return From; 2614 return From;
2615 } 2615 }
2616 if (Variable *Var = llvm::dyn_cast<Variable>(From)) { 2616 if (Variable *Var = llvm::dyn_cast<Variable>(From)) {
2617 // We need a new physical register for the operand if: 2617 // We need a new physical register for the operand if:
2618 // Mem is not allowed and Var->getRegNum() is unknown, or 2618 // Mem is not allowed and Var isn't guaranteed a physical
2619 // register, or
2619 // RegNum is required and Var->getRegNum() doesn't match. 2620 // RegNum is required and Var->getRegNum() doesn't match.
2620 if ((!(Allowed & Legal_Mem) && !Var->hasReg()) || 2621 bool WillHaveRegister =
2622 (Var->hasReg() || Var->getWeight() == RegWeight::Inf);
2623 if ((!(Allowed & Legal_Mem) && !WillHaveRegister) ||
2621 (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) { 2624 (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
2622 Variable *Reg = copyToReg(From, RegNum); 2625 Variable *Reg = copyToReg(From, RegNum);
2623 if (RegNum == Variable::NoRegister) { 2626 if (RegNum == Variable::NoRegister) {
2624 Reg->setPreferredRegister(Var, AllowOverlap); 2627 Reg->setPreferredRegister(Var, AllowOverlap);
2625 } 2628 }
2626 From = Reg; 2629 From = Reg;
2627 } 2630 }
2628 return From; 2631 return From;
2629 } 2632 }
2630 llvm_unreachable("Unhandled operand kind in legalize()"); 2633 llvm_unreachable("Unhandled operand kind in legalize()");
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2835 for (SizeT i = 0; i < Size; ++i) { 2838 for (SizeT i = 0; i < Size; ++i) {
2836 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n"; 2839 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n";
2837 } 2840 }
2838 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; 2841 Str << "\t.size\t" << MangledName << ", " << Size << "\n";
2839 } 2842 }
2840 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName 2843 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName
2841 << "\n"; 2844 << "\n";
2842 } 2845 }
2843 2846
2844 } // end of namespace Ice 2847 } // end of namespace Ice
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