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Side by Side Diff: src/IceOperand.h

Issue 372113005: Add support for passing and returning vectors in accordance with the x86 calling convention. (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Created 6 years, 5 months ago
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1 //===- subzero/src/IceOperand.h - High-level operands -----------*- C++ -*-===// 1 //===- subzero/src/IceOperand.h - High-level operands -----------*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file declares the Operand class and its target-independent 10 // This file declares the Operand class and its target-independent
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334 void setDefinition(Inst *Inst, const CfgNode *Node); 334 void setDefinition(Inst *Inst, const CfgNode *Node);
335 void replaceDefinition(Inst *Inst, const CfgNode *Node); 335 void replaceDefinition(Inst *Inst, const CfgNode *Node);
336 336
337 const CfgNode *getLocalUseNode() const { return DefNode; } 337 const CfgNode *getLocalUseNode() const { return DefNode; }
338 bool isMultiblockLife() const { return (DefNode == NULL); } 338 bool isMultiblockLife() const { return (DefNode == NULL); }
339 void setUse(const Inst *Inst, const CfgNode *Node); 339 void setUse(const Inst *Inst, const CfgNode *Node);
340 340
341 bool getIsArg() const { return IsArgument; } 341 bool getIsArg() const { return IsArgument; }
342 void setIsArg(Cfg *Func); 342 void setIsArg(Cfg *Func);
343 343
344 enum ArgLocInfo {
345 NoArgLoc,
346 RegisterArgLoc,
347 StackArgLoc
348 };
349
350 ArgLocInfo getArgLoc() const { return ArgLoc; }
351 void setArgLoc(ArgLocInfo Loc) { ArgLoc = Loc; }
352
344 int32_t getStackOffset() const { return StackOffset; } 353 int32_t getStackOffset() const { return StackOffset; }
345 void setStackOffset(int32_t Offset) { StackOffset = Offset; } 354 void setStackOffset(int32_t Offset) { StackOffset = Offset; }
346 355
347 static const int32_t NoRegister = -1; 356 static const int32_t NoRegister = -1;
348 bool hasReg() const { return getRegNum() != NoRegister; } 357 bool hasReg() const { return getRegNum() != NoRegister; }
349 int32_t getRegNum() const { return RegNum; } 358 int32_t getRegNum() const { return RegNum; }
350 void setRegNum(int32_t NewRegNum) { 359 void setRegNum(int32_t NewRegNum) {
351 // Regnum shouldn't be set more than once. 360 // Regnum shouldn't be set more than once.
352 assert(!hasReg() || RegNum == NewRegNum); 361 assert(!hasReg() || RegNum == NewRegNum);
353 RegNum = NewRegNum; 362 RegNum = NewRegNum;
354 } 363 }
355 bool hasRegTmp() const { return getRegNumTmp() != NoRegister; } 364 bool hasRegTmp() const { return getRegNumTmp() != NoRegister; }
356 int32_t getRegNumTmp() const { return RegNumTmp; } 365 int32_t getRegNumTmp() const { return RegNumTmp; }
357 void setRegNumTmp(int32_t NewRegNum) { RegNumTmp = NewRegNum; } 366 void setRegNumTmp(int32_t NewRegNum) { RegNumTmp = NewRegNum; }
358 367
368 Variable *getHomeRegister() const { return HomeRegister; }
369 void setHomeRegister(Variable *NewHomeRegister) {
370 HomeRegister = NewHomeRegister;
371 }
372
359 RegWeight getWeight() const { return Weight; } 373 RegWeight getWeight() const { return Weight; }
360 void setWeight(uint32_t NewWeight) { Weight = NewWeight; } 374 void setWeight(uint32_t NewWeight) { Weight = NewWeight; }
361 void setWeightInfinite() { Weight = RegWeight::Inf; } 375 void setWeightInfinite() { Weight = RegWeight::Inf; }
362 376
363 Variable *getPreferredRegister() const { return RegisterPreference; } 377 Variable *getPreferredRegister() const { return RegisterPreference; }
364 bool getRegisterOverlap() const { return AllowRegisterOverlap; } 378 bool getRegisterOverlap() const { return AllowRegisterOverlap; }
365 void setPreferredRegister(Variable *Prefer, bool Overlap) { 379 void setPreferredRegister(Variable *Prefer, bool Overlap) {
366 RegisterPreference = Prefer; 380 RegisterPreference = Prefer;
367 AllowRegisterOverlap = Overlap; 381 AllowRegisterOverlap = Overlap;
368 } 382 }
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403 } 417 }
404 418
405 // The destructor is public because of the asType() method. 419 // The destructor is public because of the asType() method.
406 virtual ~Variable() {} 420 virtual ~Variable() {}
407 421
408 private: 422 private:
409 Variable(Type Ty, const CfgNode *Node, SizeT Index, const IceString &Name) 423 Variable(Type Ty, const CfgNode *Node, SizeT Index, const IceString &Name)
410 : Operand(kVariable, Ty), Number(Index), Name(Name), DefInst(NULL), 424 : Operand(kVariable, Ty), Number(Index), Name(Name), DefInst(NULL),
411 DefNode(Node), IsArgument(false), StackOffset(0), RegNum(NoRegister), 425 DefNode(Node), IsArgument(false), StackOffset(0), RegNum(NoRegister),
412 RegNumTmp(NoRegister), Weight(1), RegisterPreference(NULL), 426 RegNumTmp(NoRegister), Weight(1), RegisterPreference(NULL),
413 AllowRegisterOverlap(false), LoVar(NULL), HiVar(NULL) { 427 AllowRegisterOverlap(false), LoVar(NULL), HiVar(NULL),
428 ArgLoc(NoArgLoc), HomeRegister(NULL) {
414 Vars = VarsReal; 429 Vars = VarsReal;
415 Vars[0] = this; 430 Vars[0] = this;
416 NumVars = 1; 431 NumVars = 1;
417 } 432 }
418 Variable(const Variable &) LLVM_DELETED_FUNCTION; 433 Variable(const Variable &) LLVM_DELETED_FUNCTION;
419 Variable &operator=(const Variable &) LLVM_DELETED_FUNCTION; 434 Variable &operator=(const Variable &) LLVM_DELETED_FUNCTION;
420 // Number is unique across all variables, and is used as a 435 // Number is unique across all variables, and is used as a
421 // (bit)vector index for liveness analysis. 436 // (bit)vector index for liveness analysis.
422 const SizeT Number; 437 const SizeT Number;
423 // Name is optional. 438 // Name is optional.
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455 LiveRange Live; 470 LiveRange Live;
456 // LoVar and HiVar are needed for lowering from 64 to 32 bits. When 471 // LoVar and HiVar are needed for lowering from 64 to 32 bits. When
457 // lowering from I64 to I32 on a 32-bit architecture, we split the 472 // lowering from I64 to I32 on a 32-bit architecture, we split the
458 // variable into two machine-size pieces. LoVar is the low-order 473 // variable into two machine-size pieces. LoVar is the low-order
459 // machine-size portion, and HiVar is the remaining high-order 474 // machine-size portion, and HiVar is the remaining high-order
460 // portion. TODO: It's wasteful to penalize all variables on all 475 // portion. TODO: It's wasteful to penalize all variables on all
461 // targets this way; use a sparser representation. It's also 476 // targets this way; use a sparser representation. It's also
462 // wasteful for a 64-bit target. 477 // wasteful for a 64-bit target.
463 Variable *LoVar; 478 Variable *LoVar;
464 Variable *HiVar; 479 Variable *HiVar;
480 // ArgLoc records the assignment of the argument (stack or register)
481 // if this value is an argument.
482 ArgLocInfo ArgLoc;
483 // HomeRegister is the home register.
484 Variable *HomeRegister;
465 // VarsReal (and Operand::Vars) are set up such that Vars[0] == 485 // VarsReal (and Operand::Vars) are set up such that Vars[0] ==
466 // this. 486 // this.
467 Variable *VarsReal[1]; 487 Variable *VarsReal[1];
468 }; 488 };
469 489
470 } // end of namespace Ice 490 } // end of namespace Ice
471 491
472 #endif // SUBZERO_SRC_ICEOPERAND_H 492 #endif // SUBZERO_SRC_ICEOPERAND_H
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