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Unified Diff: src/mips64/simulator-mips64.h

Issue 371923006: Add mips64 port. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Rebase Created 6 years, 5 months ago
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Index: src/mips64/simulator-mips64.h
diff --git a/src/mips/simulator-mips.h b/src/mips64/simulator-mips64.h
similarity index 72%
copy from src/mips/simulator-mips.h
copy to src/mips64/simulator-mips64.h
index 4c84b86db6591d33650d4f4e36a8fe5a9b857e2b..6bad6324a09fa3d1462aabbc7b2458fa17a775d3 100644
--- a/src/mips/simulator-mips.h
+++ b/src/mips64/simulator-mips64.h
@@ -14,7 +14,7 @@
#define V8_MIPS_SIMULATOR_MIPS_H_
#include "src/allocation.h"
-#include "src/mips/constants-mips.h"
+#include "src/mips64/constants-mips64.h"
#if !defined(USE_SIMULATOR)
// Running without a simulator on a native mips platform.
@@ -26,18 +26,47 @@ namespace internal {
#define CALL_GENERATED_CODE(entry, p0, p1, p2, p3, p4) \
entry(p0, p1, p2, p3, p4)
-typedef int (*mips_regexp_matcher)(String*, int, const byte*, const byte*,
- void*, int*, int, Address, int, Isolate*);
-
// Call the generated regexp code directly. The code at the entry address
// should act as a function matching the type arm_regexp_matcher.
-// The fifth argument is a dummy that reserves the space used for
+// The fifth (or ninth) argument is a dummy that reserves the space used for
// the return address added by the ExitFrame in native calls.
+#ifdef MIPS_ABI_N64
+typedef int (*mips_regexp_matcher)(String* input,
+ int64_t start_offset,
+ const byte* input_start,
+ const byte* input_end,
+ int* output,
+ int64_t output_size,
+ Address stack_base,
+ int64_t direct_call,
+ void* return_address,
+ Isolate* isolate);
+
+#define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
+ (FUNCTION_CAST<mips_regexp_matcher>(entry)( \
+ p0, p1, p2, p3, p4, p5, p6, p7, NULL, p8))
+
+#else // O32 Abi.
+
+typedef int (*mips_regexp_matcher)(String* input,
+ int32_t start_offset,
+ const byte* input_start,
+ const byte* input_end,
+ void* return_address,
+ int* output,
+ int32_t output_size,
+ Address stack_base,
+ int32_t direct_call,
+ Isolate* isolate);
+
#define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
(FUNCTION_CAST<mips_regexp_matcher>(entry)( \
p0, p1, p2, p3, NULL, p4, p5, p6, p7, p8))
+#endif // MIPS_ABI_N64
+
+
// The stack limit beyond which we will throw stack overflow errors in
// generated code. Because generated code on mips uses the C stack, we
// just use the C stack limit.
@@ -119,8 +148,8 @@ class Simulator {
zero_reg = 0,
at,
v0, v1,
- a0, a1, a2, a3,
- t0, t1, t2, t3, t4, t5, t6, t7,
+ a0, a1, a2, a3, a4, a5, a6, a7,
+ t0, t1, t2, t3,
s0, s1, s2, s3, s4, s5, s6, s7,
t8, t9,
k0, k1,
@@ -157,25 +186,31 @@ class Simulator {
// Accessors for register state. Reading the pc value adheres to the MIPS
// architecture specification and is off by a 8 from the currently executing
// instruction.
- void set_register(int reg, int32_t value);
+ void set_register(int reg, int64_t value);
+ void set_register_word(int reg, int32_t value);
void set_dw_register(int dreg, const int* dbl);
- int32_t get_register(int reg) const;
+ int64_t get_register(int reg) const;
double get_double_from_register_pair(int reg);
// Same for FPURegisters.
- void set_fpu_register(int fpureg, int32_t value);
+ void set_fpu_register(int fpureg, int64_t value);
+ void set_fpu_register_word(int fpureg, int32_t value);
+ void set_fpu_register_hi_word(int fpureg, int32_t value);
void set_fpu_register_float(int fpureg, float value);
void set_fpu_register_double(int fpureg, double value);
- int32_t get_fpu_register(int fpureg) const;
- int64_t get_fpu_register_long(int fpureg) const;
+ int64_t get_fpu_register(int fpureg) const;
+ int32_t get_fpu_register_word(int fpureg) const;
+ int32_t get_fpu_register_signed_word(int fpureg) const;
+ uint32_t get_fpu_register_hi_word(int fpureg) const;
float get_fpu_register_float(int fpureg) const;
double get_fpu_register_double(int fpureg) const;
void set_fcsr_bit(uint32_t cc, bool value);
bool test_fcsr_bit(uint32_t cc);
bool set_fcsr_round_error(double original, double rounded);
+ bool set_fcsr_round64_error(double original, double rounded);
// Special case of set_register and get_register to access the raw PC value.
- void set_pc(int32_t value);
- int32_t get_pc() const;
+ void set_pc(int64_t value);
+ int64_t get_pc() const;
Address get_sp() {
return reinterpret_cast<Address>(static_cast<intptr_t>(get_register(sp)));
@@ -193,7 +228,7 @@ class Simulator {
// V8 generally calls into generated JS code with 5 parameters and into
// generated RegExp code with 7 parameters. This is a convenience function,
// which sets up the simulator state and grabs the result on return.
- int32_t Call(byte* entry, int argument_count, ...);
+ int64_t Call(byte* entry, int argument_count, ...);
// Alternative: call a 2-argument double function.
double CallFP(byte* entry, double d0, double d1);
@@ -233,22 +268,41 @@ class Simulator {
void Format(Instruction* instr, const char* format);
// Read and write memory.
- inline uint32_t ReadBU(int32_t addr);
- inline int32_t ReadB(int32_t addr);
- inline void WriteB(int32_t addr, uint8_t value);
- inline void WriteB(int32_t addr, int8_t value);
+ inline uint32_t ReadBU(int64_t addr);
+ inline int32_t ReadB(int64_t addr);
+ inline void WriteB(int64_t addr, uint8_t value);
+ inline void WriteB(int64_t addr, int8_t value);
- inline uint16_t ReadHU(int32_t addr, Instruction* instr);
- inline int16_t ReadH(int32_t addr, Instruction* instr);
+ inline uint16_t ReadHU(int64_t addr, Instruction* instr);
+ inline int16_t ReadH(int64_t addr, Instruction* instr);
// Note: Overloaded on the sign of the value.
- inline void WriteH(int32_t addr, uint16_t value, Instruction* instr);
- inline void WriteH(int32_t addr, int16_t value, Instruction* instr);
-
- inline int ReadW(int32_t addr, Instruction* instr);
- inline void WriteW(int32_t addr, int value, Instruction* instr);
+ inline void WriteH(int64_t addr, uint16_t value, Instruction* instr);
+ inline void WriteH(int64_t addr, int16_t value, Instruction* instr);
+
+ inline uint32_t ReadWU(int64_t addr, Instruction* instr);
+ inline int32_t ReadW(int64_t addr, Instruction* instr);
+ inline void WriteW(int64_t addr, int32_t value, Instruction* instr);
+ inline int64_t Read2W(int64_t addr, Instruction* instr);
+ inline void Write2W(int64_t addr, int64_t value, Instruction* instr);
+
+ inline double ReadD(int64_t addr, Instruction* instr);
+ inline void WriteD(int64_t addr, double value, Instruction* instr);
+
+ // Helper for debugging memory access.
+ inline void DieOrDebug();
+
+ // Helpers for data value tracing.
+ enum TraceType {
+ BYTE,
+ HALF,
+ WORD,
+ DWORD
+ // DFLOAT - Floats may have printing issues due to paired lwc1's
+ };
- inline double ReadD(int32_t addr, Instruction* instr);
- inline void WriteD(int32_t addr, double value, Instruction* instr);
+ void TraceRegWr(int64_t value);
+ void TraceMemWr(int64_t addr, int64_t value, TraceType t);
+ void TraceMemRd(int64_t addr, int64_t value);
// Operations depending on endianness.
// Get Double Higher / Lower word.
@@ -263,12 +317,14 @@ class Simulator {
// Helper function for DecodeTypeRegister.
void ConfigureTypeRegister(Instruction* instr,
- int32_t* alu_out,
+ int64_t* alu_out,
int64_t* i64hilo,
uint64_t* u64hilo,
- int32_t* next_pc,
- int32_t* return_addr_reg,
- bool* do_interrupt);
+ int64_t* next_pc,
+ int64_t* return_addr_reg,
+ bool* do_interrupt,
+ int64_t* result128H,
+ int64_t* result128L);
void DecodeTypeImmediate(Instruction* instr);
void DecodeTypeJump(Instruction* instr);
@@ -277,15 +333,15 @@ class Simulator {
void SoftwareInterrupt(Instruction* instr);
// Stop helper functions.
- bool IsWatchpoint(uint32_t code);
- void PrintWatchpoint(uint32_t code);
- void HandleStop(uint32_t code, Instruction* instr);
+ bool IsWatchpoint(uint64_t code);
+ void PrintWatchpoint(uint64_t code);
+ void HandleStop(uint64_t code, Instruction* instr);
bool IsStopInstruction(Instruction* instr);
- bool IsEnabledStop(uint32_t code);
- void EnableStop(uint32_t code);
- void DisableStop(uint32_t code);
- void IncreaseStopCounter(uint32_t code);
- void PrintStopInfo(uint32_t code);
+ bool IsEnabledStop(uint64_t code);
+ void EnableStop(uint64_t code);
+ void DisableStop(uint64_t code);
+ void IncreaseStopCounter(uint64_t code);
+ void PrintStopInfo(uint64_t code);
// Executes one instruction.
@@ -336,19 +392,20 @@ class Simulator {
// Architecture state.
// Registers.
- int32_t registers_[kNumSimuRegisters];
+ int64_t registers_[kNumSimuRegisters];
// Coprocessor Registers.
- int32_t FPUregisters_[kNumFPURegisters];
+ int64_t FPUregisters_[kNumFPURegisters];
// FPU control register.
uint32_t FCSR_;
// Simulator support.
// Allocate 1MB for stack.
- static const size_t stack_size_ = 1 * 1024*1024;
+ size_t stack_size_;
char* stack_;
bool pc_modified_;
- int icount_;
+ int64_t icount_;
int break_count_;
+ EmbeddedVector<char, 128> trace_buf_;
// Debugger input.
char* last_debugger_input_;
@@ -383,9 +440,15 @@ class Simulator {
reinterpret_cast<Object*>(Simulator::current(Isolate::Current())->Call( \
FUNCTION_ADDR(entry), 5, p0, p1, p2, p3, p4))
+#ifdef MIPS_ABI_N64
+#define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
+ Simulator::current(Isolate::Current())->Call( \
+ entry, 10, p0, p1, p2, p3, p4, p5, p6, p7, NULL, p8)
+#else // Must be O32 Abi.
#define CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) \
Simulator::current(Isolate::Current())->Call( \
entry, 10, p0, p1, p2, p3, NULL, p4, p5, p6, p7, p8)
+#endif // MIPS_ABI_N64
// The simulator has its own stack. Thus it has a different stack limit from
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