OLD | NEW |
1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> | 5 #include <limits.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdlib.h> | 7 #include <stdlib.h> |
8 #include <cmath> | 8 #include <cmath> |
9 | 9 |
10 #include "src/v8.h" | 10 #include "src/v8.h" |
11 | 11 |
12 #if V8_TARGET_ARCH_MIPS | 12 #if V8_TARGET_ARCH_MIPS64 |
13 | 13 |
14 #include "src/assembler.h" | 14 #include "src/assembler.h" |
15 #include "src/disasm.h" | 15 #include "src/disasm.h" |
16 #include "src/globals.h" // Need the BitCast. | 16 #include "src/globals.h" // Need the BitCast. |
17 #include "src/mips/constants-mips.h" | 17 #include "src/mips64/constants-mips64.h" |
18 #include "src/mips/simulator-mips.h" | 18 #include "src/mips64/simulator-mips64.h" |
19 | 19 |
20 | 20 |
21 // Only build the simulator if not compiling for real MIPS hardware. | 21 // Only build the simulator if not compiling for real MIPS hardware. |
22 #if defined(USE_SIMULATOR) | 22 #if defined(USE_SIMULATOR) |
23 | 23 |
24 namespace v8 { | 24 namespace v8 { |
25 namespace internal { | 25 namespace internal { |
26 | 26 |
27 // Utils functions. | 27 // Utils functions. |
28 bool HaveSameSign(int32_t a, int32_t b) { | 28 bool HaveSameSign(int64_t a, int64_t b) { |
29 return ((a ^ b) >= 0); | 29 return ((a ^ b) >= 0); |
30 } | 30 } |
31 | 31 |
32 | 32 |
33 uint32_t get_fcsr_condition_bit(uint32_t cc) { | 33 uint32_t get_fcsr_condition_bit(uint32_t cc) { |
34 if (cc == 0) { | 34 if (cc == 0) { |
35 return 23; | 35 return 23; |
36 } else { | 36 } else { |
37 return 24 + cc; | 37 return 24 + cc; |
38 } | 38 } |
39 } | 39 } |
40 | 40 |
41 | 41 |
| 42 static int64_t MultiplyHighSigned(int64_t u, int64_t v) { |
| 43 uint64_t u0, v0, w0; |
| 44 int64_t u1, v1, w1, w2, t; |
| 45 |
| 46 u0 = u & 0xffffffffL; |
| 47 u1 = u >> 32; |
| 48 v0 = v & 0xffffffffL; |
| 49 v1 = v >> 32; |
| 50 |
| 51 w0 = u0 * v0; |
| 52 t = u1 * v0 + (w0 >> 32); |
| 53 w1 = t & 0xffffffffL; |
| 54 w2 = t >> 32; |
| 55 w1 = u0 * v1 + w1; |
| 56 |
| 57 return u1 * v1 + w2 + (w1 >> 32); |
| 58 } |
| 59 |
| 60 |
42 // This macro provides a platform independent use of sscanf. The reason for | 61 // This macro provides a platform independent use of sscanf. The reason for |
43 // SScanF not being implemented in a platform independent was through | 62 // SScanF not being implemented in a platform independent was through |
44 // ::v8::internal::OS in the same way as SNPrintF is that the Windows C Run-Time | 63 // ::v8::internal::OS in the same way as SNPrintF is that the Windows C Run-Time |
45 // Library does not provide vsscanf. | 64 // Library does not provide vsscanf. |
46 #define SScanF sscanf // NOLINT | 65 #define SScanF sscanf // NOLINT |
47 | 66 |
48 // The MipsDebugger class is used by the simulator while debugging simulated | 67 // The MipsDebugger class is used by the simulator while debugging simulated |
49 // code. | 68 // code. |
50 class MipsDebugger { | 69 class MipsDebugger { |
51 public: | 70 public: |
52 explicit MipsDebugger(Simulator* sim) : sim_(sim) { } | 71 explicit MipsDebugger(Simulator* sim) : sim_(sim) { } |
53 ~MipsDebugger(); | 72 ~MipsDebugger(); |
54 | 73 |
55 void Stop(Instruction* instr); | 74 void Stop(Instruction* instr); |
56 void Debug(); | 75 void Debug(); |
57 // Print all registers with a nice formatting. | 76 // Print all registers with a nice formatting. |
58 void PrintAllRegs(); | 77 void PrintAllRegs(); |
59 void PrintAllRegsIncludingFPU(); | 78 void PrintAllRegsIncludingFPU(); |
60 | 79 |
61 private: | 80 private: |
62 // We set the breakpoint code to 0xfffff to easily recognize it. | 81 // We set the breakpoint code to 0xfffff to easily recognize it. |
63 static const Instr kBreakpointInstr = SPECIAL | BREAK | 0xfffff << 6; | 82 static const Instr kBreakpointInstr = SPECIAL | BREAK | 0xfffff << 6; |
64 static const Instr kNopInstr = 0x0; | 83 static const Instr kNopInstr = 0x0; |
65 | 84 |
66 Simulator* sim_; | 85 Simulator* sim_; |
67 | 86 |
68 int32_t GetRegisterValue(int regnum); | 87 int64_t GetRegisterValue(int regnum); |
69 int32_t GetFPURegisterValueInt(int regnum); | 88 int64_t GetFPURegisterValue(int regnum); |
70 int64_t GetFPURegisterValueLong(int regnum); | |
71 float GetFPURegisterValueFloat(int regnum); | 89 float GetFPURegisterValueFloat(int regnum); |
72 double GetFPURegisterValueDouble(int regnum); | 90 double GetFPURegisterValueDouble(int regnum); |
73 bool GetValue(const char* desc, int32_t* value); | 91 bool GetValue(const char* desc, int64_t* value); |
74 | 92 |
75 // Set or delete a breakpoint. Returns true if successful. | 93 // Set or delete a breakpoint. Returns true if successful. |
76 bool SetBreakpoint(Instruction* breakpc); | 94 bool SetBreakpoint(Instruction* breakpc); |
77 bool DeleteBreakpoint(Instruction* breakpc); | 95 bool DeleteBreakpoint(Instruction* breakpc); |
78 | 96 |
79 // Undo and redo all breakpoints. This is needed to bracket disassembly and | 97 // Undo and redo all breakpoints. This is needed to bracket disassembly and |
80 // execution to skip past breakpoints when run from the debugger. | 98 // execution to skip past breakpoints when run from the debugger. |
81 void UndoBreakpoints(); | 99 void UndoBreakpoints(); |
82 void RedoBreakpoints(); | 100 void RedoBreakpoints(); |
83 }; | 101 }; |
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115 | 133 |
116 if (strlen(msg) > 0) { | 134 if (strlen(msg) > 0) { |
117 if (coverage_log != NULL) { | 135 if (coverage_log != NULL) { |
118 fprintf(coverage_log, "%s\n", str); | 136 fprintf(coverage_log, "%s\n", str); |
119 fflush(coverage_log); | 137 fflush(coverage_log); |
120 } | 138 } |
121 // Overwrite the instruction and address with nops. | 139 // Overwrite the instruction and address with nops. |
122 instr->SetInstructionBits(kNopInstr); | 140 instr->SetInstructionBits(kNopInstr); |
123 reinterpret_cast<Instr*>(msg_address)->SetInstructionBits(kNopInstr); | 141 reinterpret_cast<Instr*>(msg_address)->SetInstructionBits(kNopInstr); |
124 } | 142 } |
125 sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstructionSize); | 143 // TODO(yuyin): 2 -> 3? |
| 144 sim_->set_pc(sim_->get_pc() + 3 * Instruction::kInstructionSize); |
126 } | 145 } |
127 | 146 |
128 | 147 |
129 #else // GENERATED_CODE_COVERAGE | 148 #else // GENERATED_CODE_COVERAGE |
130 | 149 |
131 #define UNSUPPORTED() printf("Unsupported instruction.\n"); | 150 #define UNSUPPORTED() printf("Unsupported instruction.\n"); |
132 | 151 |
133 static void InitializeCoverage() {} | 152 static void InitializeCoverage() {} |
134 | 153 |
135 | 154 |
136 void MipsDebugger::Stop(Instruction* instr) { | 155 void MipsDebugger::Stop(Instruction* instr) { |
137 // Get the stop code. | 156 // Get the stop code. |
138 uint32_t code = instr->Bits(25, 6); | 157 uint32_t code = instr->Bits(25, 6); |
139 // Retrieve the encoded address, which comes just after this stop. | 158 // Retrieve the encoded address, which comes just after this stop. |
140 char* msg = *reinterpret_cast<char**>(sim_->get_pc() + | 159 char* msg = *reinterpret_cast<char**>(sim_->get_pc() + |
141 Instruction::kInstrSize); | 160 Instruction::kInstrSize); |
142 // Update this stop description. | 161 // Update this stop description. |
143 if (!sim_->watched_stops_[code].desc) { | 162 if (!sim_->watched_stops_[code].desc) { |
144 sim_->watched_stops_[code].desc = msg; | 163 sim_->watched_stops_[code].desc = msg; |
145 } | 164 } |
146 PrintF("Simulator hit %s (%u)\n", msg, code); | 165 PrintF("Simulator hit %s (%u)\n", msg, code); |
147 sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstrSize); | 166 // TODO(yuyin): 2 -> 3? |
| 167 sim_->set_pc(sim_->get_pc() + 3 * Instruction::kInstrSize); |
148 Debug(); | 168 Debug(); |
149 } | 169 } |
150 #endif // GENERATED_CODE_COVERAGE | 170 #endif // GENERATED_CODE_COVERAGE |
151 | 171 |
152 | 172 |
153 int32_t MipsDebugger::GetRegisterValue(int regnum) { | 173 int64_t MipsDebugger::GetRegisterValue(int regnum) { |
154 if (regnum == kNumSimuRegisters) { | 174 if (regnum == kNumSimuRegisters) { |
155 return sim_->get_pc(); | 175 return sim_->get_pc(); |
156 } else { | 176 } else { |
157 return sim_->get_register(regnum); | 177 return sim_->get_register(regnum); |
158 } | 178 } |
159 } | 179 } |
160 | 180 |
161 | 181 |
162 int32_t MipsDebugger::GetFPURegisterValueInt(int regnum) { | 182 int64_t MipsDebugger::GetFPURegisterValue(int regnum) { |
163 if (regnum == kNumFPURegisters) { | 183 if (regnum == kNumFPURegisters) { |
164 return sim_->get_pc(); | 184 return sim_->get_pc(); |
165 } else { | 185 } else { |
166 return sim_->get_fpu_register(regnum); | 186 return sim_->get_fpu_register(regnum); |
167 } | 187 } |
168 } | 188 } |
169 | 189 |
170 | 190 |
171 int64_t MipsDebugger::GetFPURegisterValueLong(int regnum) { | |
172 if (regnum == kNumFPURegisters) { | |
173 return sim_->get_pc(); | |
174 } else { | |
175 return sim_->get_fpu_register_long(regnum); | |
176 } | |
177 } | |
178 | |
179 | |
180 float MipsDebugger::GetFPURegisterValueFloat(int regnum) { | 191 float MipsDebugger::GetFPURegisterValueFloat(int regnum) { |
181 if (regnum == kNumFPURegisters) { | 192 if (regnum == kNumFPURegisters) { |
182 return sim_->get_pc(); | 193 return sim_->get_pc(); |
183 } else { | 194 } else { |
184 return sim_->get_fpu_register_float(regnum); | 195 return sim_->get_fpu_register_float(regnum); |
185 } | 196 } |
186 } | 197 } |
187 | 198 |
188 | 199 |
189 double MipsDebugger::GetFPURegisterValueDouble(int regnum) { | 200 double MipsDebugger::GetFPURegisterValueDouble(int regnum) { |
190 if (regnum == kNumFPURegisters) { | 201 if (regnum == kNumFPURegisters) { |
191 return sim_->get_pc(); | 202 return sim_->get_pc(); |
192 } else { | 203 } else { |
193 return sim_->get_fpu_register_double(regnum); | 204 return sim_->get_fpu_register_double(regnum); |
194 } | 205 } |
195 } | 206 } |
196 | 207 |
197 | 208 |
198 bool MipsDebugger::GetValue(const char* desc, int32_t* value) { | 209 bool MipsDebugger::GetValue(const char* desc, int64_t* value) { |
199 int regnum = Registers::Number(desc); | 210 int regnum = Registers::Number(desc); |
200 int fpuregnum = FPURegisters::Number(desc); | 211 int fpuregnum = FPURegisters::Number(desc); |
201 | 212 |
202 if (regnum != kInvalidRegister) { | 213 if (regnum != kInvalidRegister) { |
203 *value = GetRegisterValue(regnum); | 214 *value = GetRegisterValue(regnum); |
204 return true; | 215 return true; |
205 } else if (fpuregnum != kInvalidFPURegister) { | 216 } else if (fpuregnum != kInvalidFPURegister) { |
206 *value = GetFPURegisterValueInt(fpuregnum); | 217 *value = GetFPURegisterValue(fpuregnum); |
207 return true; | 218 return true; |
208 } else if (strncmp(desc, "0x", 2) == 0) { | 219 } else if (strncmp(desc, "0x", 2) == 0) { |
209 return SScanF(desc, "%x", reinterpret_cast<uint32_t*>(value)) == 1; | 220 return SScanF(desc + 2, "%" SCNx64, |
| 221 reinterpret_cast<uint64_t*>(value)) == 1; |
210 } else { | 222 } else { |
211 return SScanF(desc, "%i", value) == 1; | 223 return SScanF(desc, "%" SCNu64, reinterpret_cast<uint64_t*>(value)) == 1; |
212 } | 224 } |
213 return false; | 225 return false; |
214 } | 226 } |
215 | 227 |
216 | 228 |
217 bool MipsDebugger::SetBreakpoint(Instruction* breakpc) { | 229 bool MipsDebugger::SetBreakpoint(Instruction* breakpc) { |
218 // Check if a breakpoint can be set. If not return without any side-effects. | 230 // Check if a breakpoint can be set. If not return without any side-effects. |
219 if (sim_->break_pc_ != NULL) { | 231 if (sim_->break_pc_ != NULL) { |
220 return false; | 232 return false; |
221 } | 233 } |
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252 sim_->break_pc_->SetInstructionBits(kBreakpointInstr); | 264 sim_->break_pc_->SetInstructionBits(kBreakpointInstr); |
253 } | 265 } |
254 } | 266 } |
255 | 267 |
256 | 268 |
257 void MipsDebugger::PrintAllRegs() { | 269 void MipsDebugger::PrintAllRegs() { |
258 #define REG_INFO(n) Registers::Name(n), GetRegisterValue(n), GetRegisterValue(n) | 270 #define REG_INFO(n) Registers::Name(n), GetRegisterValue(n), GetRegisterValue(n) |
259 | 271 |
260 PrintF("\n"); | 272 PrintF("\n"); |
261 // at, v0, a0. | 273 // at, v0, a0. |
262 PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n", | 274 PrintF("%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\n", |
263 REG_INFO(1), REG_INFO(2), REG_INFO(4)); | 275 REG_INFO(1), REG_INFO(2), REG_INFO(4)); |
264 // v1, a1. | 276 // v1, a1. |
265 PrintF("%26s\t%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n", | 277 PrintF("%34s\t%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\n", |
266 "", REG_INFO(3), REG_INFO(5)); | 278 "", REG_INFO(3), REG_INFO(5)); |
267 // a2. | 279 // a2. |
268 PrintF("%26s\t%26s\t%3s: 0x%08x %10d\n", "", "", REG_INFO(6)); | 280 PrintF("%34s\t%34s\t%3s: 0x%016lx %14ld\n", "", "", REG_INFO(6)); |
269 // a3. | 281 // a3. |
270 PrintF("%26s\t%26s\t%3s: 0x%08x %10d\n", "", "", REG_INFO(7)); | 282 PrintF("%34s\t%34s\t%3s: 0x%016lx %14ld\n", "", "", REG_INFO(7)); |
271 PrintF("\n"); | 283 PrintF("\n"); |
272 // t0-t7, s0-s7 | 284 // a4-t3, s0-s7 |
273 for (int i = 0; i < 8; i++) { | 285 for (int i = 0; i < 8; i++) { |
274 PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n", | 286 PrintF("%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\n", |
275 REG_INFO(8+i), REG_INFO(16+i)); | 287 REG_INFO(8+i), REG_INFO(16+i)); |
276 } | 288 } |
277 PrintF("\n"); | 289 PrintF("\n"); |
278 // t8, k0, LO. | 290 // t8, k0, LO. |
279 PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n", | 291 PrintF("%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\n", |
280 REG_INFO(24), REG_INFO(26), REG_INFO(32)); | 292 REG_INFO(24), REG_INFO(26), REG_INFO(32)); |
281 // t9, k1, HI. | 293 // t9, k1, HI. |
282 PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n", | 294 PrintF("%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\n", |
283 REG_INFO(25), REG_INFO(27), REG_INFO(33)); | 295 REG_INFO(25), REG_INFO(27), REG_INFO(33)); |
284 // sp, fp, gp. | 296 // sp, fp, gp. |
285 PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n", | 297 PrintF("%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\n", |
286 REG_INFO(29), REG_INFO(30), REG_INFO(28)); | 298 REG_INFO(29), REG_INFO(30), REG_INFO(28)); |
287 // pc. | 299 // pc. |
288 PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n", | 300 PrintF("%3s: 0x%016lx %14ld\t%3s: 0x%016lx %14ld\n", |
289 REG_INFO(31), REG_INFO(34)); | 301 REG_INFO(31), REG_INFO(34)); |
290 | 302 |
291 #undef REG_INFO | 303 #undef REG_INFO |
292 #undef FPU_REG_INFO | 304 #undef FPU_REG_INFO |
293 } | 305 } |
294 | 306 |
295 | 307 |
296 void MipsDebugger::PrintAllRegsIncludingFPU() { | 308 void MipsDebugger::PrintAllRegsIncludingFPU() { |
297 #define FPU_REG_INFO(n) FPURegisters::Name(n), FPURegisters::Name(n+1), \ | 309 #define FPU_REG_INFO(n) FPURegisters::Name(n), \ |
298 GetFPURegisterValueInt(n+1), \ | 310 GetFPURegisterValue(n), \ |
299 GetFPURegisterValueInt(n), \ | 311 GetFPURegisterValueDouble(n) |
300 GetFPURegisterValueDouble(n) | |
301 | 312 |
302 PrintAllRegs(); | 313 PrintAllRegs(); |
303 | 314 |
304 PrintF("\n\n"); | 315 PrintF("\n\n"); |
305 // f0, f1, f2, ... f31. | 316 // f0, f1, f2, ... f31. |
306 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(0) ); | 317 // TODO(plind): consider printing 2 columns for space efficiency. |
307 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(2) ); | 318 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(0) ); |
308 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(4) ); | 319 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(1) ); |
309 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(6) ); | 320 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(2) ); |
310 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(8) ); | 321 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(3) ); |
311 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(10)); | 322 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(4) ); |
312 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(12)); | 323 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(5) ); |
313 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(14)); | 324 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(6) ); |
314 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(16)); | 325 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(7) ); |
315 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(18)); | 326 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(8) ); |
316 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(20)); | 327 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(9) ); |
317 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(22)); | 328 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(10)); |
318 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(24)); | 329 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(11)); |
319 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(26)); | 330 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(12)); |
320 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(28)); | 331 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(13)); |
321 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(30)); | 332 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(14)); |
| 333 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(15)); |
| 334 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(16)); |
| 335 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(17)); |
| 336 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(18)); |
| 337 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(19)); |
| 338 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(20)); |
| 339 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(21)); |
| 340 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(22)); |
| 341 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(23)); |
| 342 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(24)); |
| 343 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(25)); |
| 344 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(26)); |
| 345 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(27)); |
| 346 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(28)); |
| 347 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(29)); |
| 348 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(30)); |
| 349 PrintF("%3s: 0x%016lx %16.4e\n", FPU_REG_INFO(31)); |
322 | 350 |
323 #undef REG_INFO | 351 #undef REG_INFO |
324 #undef FPU_REG_INFO | 352 #undef FPU_REG_INFO |
325 } | 353 } |
326 | 354 |
327 | 355 |
328 void MipsDebugger::Debug() { | 356 void MipsDebugger::Debug() { |
329 intptr_t last_pc = -1; | 357 intptr_t last_pc = -1; |
330 bool done = false; | 358 bool done = false; |
331 | 359 |
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350 UndoBreakpoints(); | 378 UndoBreakpoints(); |
351 | 379 |
352 while (!done && (sim_->get_pc() != Simulator::end_sim_pc)) { | 380 while (!done && (sim_->get_pc() != Simulator::end_sim_pc)) { |
353 if (last_pc != sim_->get_pc()) { | 381 if (last_pc != sim_->get_pc()) { |
354 disasm::NameConverter converter; | 382 disasm::NameConverter converter; |
355 disasm::Disassembler dasm(converter); | 383 disasm::Disassembler dasm(converter); |
356 // Use a reasonably large buffer. | 384 // Use a reasonably large buffer. |
357 v8::internal::EmbeddedVector<char, 256> buffer; | 385 v8::internal::EmbeddedVector<char, 256> buffer; |
358 dasm.InstructionDecode(buffer, | 386 dasm.InstructionDecode(buffer, |
359 reinterpret_cast<byte*>(sim_->get_pc())); | 387 reinterpret_cast<byte*>(sim_->get_pc())); |
360 PrintF(" 0x%08x %s\n", sim_->get_pc(), buffer.start()); | 388 PrintF(" 0x%016lx %s\n", sim_->get_pc(), buffer.start()); |
361 last_pc = sim_->get_pc(); | 389 last_pc = sim_->get_pc(); |
362 } | 390 } |
363 char* line = ReadLine("sim> "); | 391 char* line = ReadLine("sim> "); |
364 if (line == NULL) { | 392 if (line == NULL) { |
365 break; | 393 break; |
366 } else { | 394 } else { |
367 char* last_input = sim_->last_debugger_input(); | 395 char* last_input = sim_->last_debugger_input(); |
368 if (strcmp(line, "\n") == 0 && last_input != NULL) { | 396 if (strcmp(line, "\n") == 0 && last_input != NULL) { |
369 line = last_input; | 397 line = last_input; |
370 } else { | 398 } else { |
(...skipping 18 matching lines...) Expand all Loading... |
389 PrintF("/!\\ Jumping over generated breakpoint.\n"); | 417 PrintF("/!\\ Jumping over generated breakpoint.\n"); |
390 sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize); | 418 sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize); |
391 } | 419 } |
392 } else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) { | 420 } else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) { |
393 // Execute the one instruction we broke at with breakpoints disabled. | 421 // Execute the one instruction we broke at with breakpoints disabled. |
394 sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc())); | 422 sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc())); |
395 // Leave the debugger shell. | 423 // Leave the debugger shell. |
396 done = true; | 424 done = true; |
397 } else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) { | 425 } else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) { |
398 if (argc == 2) { | 426 if (argc == 2) { |
399 int32_t value; | 427 int64_t value; |
400 float fvalue; | 428 double dvalue; |
401 if (strcmp(arg1, "all") == 0) { | 429 if (strcmp(arg1, "all") == 0) { |
402 PrintAllRegs(); | 430 PrintAllRegs(); |
403 } else if (strcmp(arg1, "allf") == 0) { | 431 } else if (strcmp(arg1, "allf") == 0) { |
404 PrintAllRegsIncludingFPU(); | 432 PrintAllRegsIncludingFPU(); |
405 } else { | 433 } else { |
406 int regnum = Registers::Number(arg1); | 434 int regnum = Registers::Number(arg1); |
407 int fpuregnum = FPURegisters::Number(arg1); | 435 int fpuregnum = FPURegisters::Number(arg1); |
408 | 436 |
409 if (regnum != kInvalidRegister) { | 437 if (regnum != kInvalidRegister) { |
410 value = GetRegisterValue(regnum); | 438 value = GetRegisterValue(regnum); |
411 PrintF("%s: 0x%08x %d \n", arg1, value, value); | 439 PrintF("%s: 0x%08lx %ld \n", arg1, value, value); |
412 } else if (fpuregnum != kInvalidFPURegister) { | 440 } else if (fpuregnum != kInvalidFPURegister) { |
413 if (fpuregnum % 2 == 1) { | 441 value = GetFPURegisterValue(fpuregnum); |
414 value = GetFPURegisterValueInt(fpuregnum); | 442 dvalue = GetFPURegisterValueDouble(fpuregnum); |
415 fvalue = GetFPURegisterValueFloat(fpuregnum); | 443 PrintF("%3s: 0x%016lx %16.4e\n", |
416 PrintF("%s: 0x%08x %11.4e\n", arg1, value, fvalue); | 444 FPURegisters::Name(fpuregnum), value, dvalue); |
417 } else { | |
418 double dfvalue; | |
419 int32_t lvalue1 = GetFPURegisterValueInt(fpuregnum); | |
420 int32_t lvalue2 = GetFPURegisterValueInt(fpuregnum + 1); | |
421 dfvalue = GetFPURegisterValueDouble(fpuregnum); | |
422 PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", | |
423 FPURegisters::Name(fpuregnum+1), | |
424 FPURegisters::Name(fpuregnum), | |
425 lvalue1, | |
426 lvalue2, | |
427 dfvalue); | |
428 } | |
429 } else { | 445 } else { |
430 PrintF("%s unrecognized\n", arg1); | 446 PrintF("%s unrecognized\n", arg1); |
431 } | 447 } |
432 } | 448 } |
433 } else { | 449 } else { |
434 if (argc == 3) { | 450 if (argc == 3) { |
435 if (strcmp(arg2, "single") == 0) { | 451 if (strcmp(arg2, "single") == 0) { |
436 int32_t value; | 452 int64_t value; |
437 float fvalue; | 453 float fvalue; |
438 int fpuregnum = FPURegisters::Number(arg1); | 454 int fpuregnum = FPURegisters::Number(arg1); |
439 | 455 |
440 if (fpuregnum != kInvalidFPURegister) { | 456 if (fpuregnum != kInvalidFPURegister) { |
441 value = GetFPURegisterValueInt(fpuregnum); | 457 value = GetFPURegisterValue(fpuregnum); |
| 458 value &= 0xffffffffUL; |
442 fvalue = GetFPURegisterValueFloat(fpuregnum); | 459 fvalue = GetFPURegisterValueFloat(fpuregnum); |
443 PrintF("%s: 0x%08x %11.4e\n", arg1, value, fvalue); | 460 PrintF("%s: 0x%08lx %11.4e\n", arg1, value, fvalue); |
444 } else { | 461 } else { |
445 PrintF("%s unrecognized\n", arg1); | 462 PrintF("%s unrecognized\n", arg1); |
446 } | 463 } |
447 } else { | 464 } else { |
448 PrintF("print <fpu register> single\n"); | 465 PrintF("print <fpu register> single\n"); |
449 } | 466 } |
450 } else { | 467 } else { |
451 PrintF("print <register> or print <fpu register> single\n"); | 468 PrintF("print <register> or print <fpu register> single\n"); |
452 } | 469 } |
453 } | 470 } |
454 } else if ((strcmp(cmd, "po") == 0) | 471 } else if ((strcmp(cmd, "po") == 0) |
455 || (strcmp(cmd, "printobject") == 0)) { | 472 || (strcmp(cmd, "printobject") == 0)) { |
456 if (argc == 2) { | 473 if (argc == 2) { |
457 int32_t value; | 474 int64_t value; |
458 OFStream os(stdout); | 475 OFStream os(stdout); |
459 if (GetValue(arg1, &value)) { | 476 if (GetValue(arg1, &value)) { |
460 Object* obj = reinterpret_cast<Object*>(value); | 477 Object* obj = reinterpret_cast<Object*>(value); |
461 os << arg1 << ": \n"; | 478 os << arg1 << ": \n"; |
462 #ifdef DEBUG | 479 #ifdef DEBUG |
463 obj->Print(os); | 480 obj->Print(os); |
464 os << "\n"; | 481 os << "\n"; |
465 #else | 482 #else |
466 os << Brief(obj) << "\n"; | 483 os << Brief(obj) << "\n"; |
467 #endif | 484 #endif |
468 } else { | 485 } else { |
469 os << arg1 << " unrecognized\n"; | 486 os << arg1 << " unrecognized\n"; |
470 } | 487 } |
471 } else { | 488 } else { |
472 PrintF("printobject <value>\n"); | 489 PrintF("printobject <value>\n"); |
473 } | 490 } |
474 } else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) { | 491 } else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) { |
475 int32_t* cur = NULL; | 492 int64_t* cur = NULL; |
476 int32_t* end = NULL; | 493 int64_t* end = NULL; |
477 int next_arg = 1; | 494 int next_arg = 1; |
478 | 495 |
479 if (strcmp(cmd, "stack") == 0) { | 496 if (strcmp(cmd, "stack") == 0) { |
480 cur = reinterpret_cast<int32_t*>(sim_->get_register(Simulator::sp)); | 497 cur = reinterpret_cast<int64_t*>(sim_->get_register(Simulator::sp)); |
481 } else { // Command "mem". | 498 } else { // Command "mem". |
482 int32_t value; | 499 int64_t value; |
483 if (!GetValue(arg1, &value)) { | 500 if (!GetValue(arg1, &value)) { |
484 PrintF("%s unrecognized\n", arg1); | 501 PrintF("%s unrecognized\n", arg1); |
485 continue; | 502 continue; |
486 } | 503 } |
487 cur = reinterpret_cast<int32_t*>(value); | 504 cur = reinterpret_cast<int64_t*>(value); |
488 next_arg++; | 505 next_arg++; |
489 } | 506 } |
490 | 507 |
491 int32_t words; | 508 int64_t words; |
492 if (argc == next_arg) { | 509 if (argc == next_arg) { |
493 words = 10; | 510 words = 10; |
494 } else { | 511 } else { |
495 if (!GetValue(argv[next_arg], &words)) { | 512 if (!GetValue(argv[next_arg], &words)) { |
496 words = 10; | 513 words = 10; |
497 } | 514 } |
498 } | 515 } |
499 end = cur + words; | 516 end = cur + words; |
500 | 517 |
501 while (cur < end) { | 518 while (cur < end) { |
502 PrintF(" 0x%08x: 0x%08x %10d", | 519 PrintF(" 0x%012lx: 0x%016lx %14ld", |
503 reinterpret_cast<intptr_t>(cur), *cur, *cur); | 520 reinterpret_cast<intptr_t>(cur), *cur, *cur); |
504 HeapObject* obj = reinterpret_cast<HeapObject*>(*cur); | 521 HeapObject* obj = reinterpret_cast<HeapObject*>(*cur); |
505 int value = *cur; | 522 int64_t value = *cur; |
506 Heap* current_heap = v8::internal::Isolate::Current()->heap(); | 523 Heap* current_heap = v8::internal::Isolate::Current()->heap(); |
507 if (((value & 1) == 0) || current_heap->Contains(obj)) { | 524 if (((value & 1) == 0) || current_heap->Contains(obj)) { |
508 PrintF(" ("); | 525 PrintF(" ("); |
509 if ((value & 1) == 0) { | 526 if ((value & 1) == 0) { |
510 PrintF("smi %d", value / 2); | 527 PrintF("smi %d", static_cast<int>(value >> 32)); |
511 } else { | 528 } else { |
512 obj->ShortPrint(); | 529 obj->ShortPrint(); |
513 } | 530 } |
514 PrintF(")"); | 531 PrintF(")"); |
515 } | 532 } |
516 PrintF("\n"); | 533 PrintF("\n"); |
517 cur++; | 534 cur++; |
518 } | 535 } |
519 | 536 |
520 } else if ((strcmp(cmd, "disasm") == 0) || | 537 } else if ((strcmp(cmd, "disasm") == 0) || |
521 (strcmp(cmd, "dpc") == 0) || | 538 (strcmp(cmd, "dpc") == 0) || |
522 (strcmp(cmd, "di") == 0)) { | 539 (strcmp(cmd, "di") == 0)) { |
523 disasm::NameConverter converter; | 540 disasm::NameConverter converter; |
524 disasm::Disassembler dasm(converter); | 541 disasm::Disassembler dasm(converter); |
525 // Use a reasonably large buffer. | 542 // Use a reasonably large buffer. |
526 v8::internal::EmbeddedVector<char, 256> buffer; | 543 v8::internal::EmbeddedVector<char, 256> buffer; |
527 | 544 |
528 byte* cur = NULL; | 545 byte* cur = NULL; |
529 byte* end = NULL; | 546 byte* end = NULL; |
530 | 547 |
531 if (argc == 1) { | 548 if (argc == 1) { |
532 cur = reinterpret_cast<byte*>(sim_->get_pc()); | 549 cur = reinterpret_cast<byte*>(sim_->get_pc()); |
533 end = cur + (10 * Instruction::kInstrSize); | 550 end = cur + (10 * Instruction::kInstrSize); |
534 } else if (argc == 2) { | 551 } else if (argc == 2) { |
535 int regnum = Registers::Number(arg1); | 552 int regnum = Registers::Number(arg1); |
536 if (regnum != kInvalidRegister || strncmp(arg1, "0x", 2) == 0) { | 553 if (regnum != kInvalidRegister || strncmp(arg1, "0x", 2) == 0) { |
537 // The argument is an address or a register name. | 554 // The argument is an address or a register name. |
538 int32_t value; | 555 int64_t value; |
539 if (GetValue(arg1, &value)) { | 556 if (GetValue(arg1, &value)) { |
540 cur = reinterpret_cast<byte*>(value); | 557 cur = reinterpret_cast<byte*>(value); |
541 // Disassemble 10 instructions at <arg1>. | 558 // Disassemble 10 instructions at <arg1>. |
542 end = cur + (10 * Instruction::kInstrSize); | 559 end = cur + (10 * Instruction::kInstrSize); |
543 } | 560 } |
544 } else { | 561 } else { |
545 // The argument is the number of instructions. | 562 // The argument is the number of instructions. |
546 int32_t value; | 563 int64_t value; |
547 if (GetValue(arg1, &value)) { | 564 if (GetValue(arg1, &value)) { |
548 cur = reinterpret_cast<byte*>(sim_->get_pc()); | 565 cur = reinterpret_cast<byte*>(sim_->get_pc()); |
549 // Disassemble <arg1> instructions. | 566 // Disassemble <arg1> instructions. |
550 end = cur + (value * Instruction::kInstrSize); | 567 end = cur + (value * Instruction::kInstrSize); |
551 } | 568 } |
552 } | 569 } |
553 } else { | 570 } else { |
554 int32_t value1; | 571 int64_t value1; |
555 int32_t value2; | 572 int64_t value2; |
556 if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) { | 573 if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) { |
557 cur = reinterpret_cast<byte*>(value1); | 574 cur = reinterpret_cast<byte*>(value1); |
558 end = cur + (value2 * Instruction::kInstrSize); | 575 end = cur + (value2 * Instruction::kInstrSize); |
559 } | 576 } |
560 } | 577 } |
561 | 578 |
562 while (cur < end) { | 579 while (cur < end) { |
563 dasm.InstructionDecode(buffer, cur); | 580 dasm.InstructionDecode(buffer, cur); |
564 PrintF(" 0x%08x %s\n", | 581 PrintF(" 0x%08lx %s\n", |
565 reinterpret_cast<intptr_t>(cur), buffer.start()); | 582 reinterpret_cast<intptr_t>(cur), buffer.start()); |
566 cur += Instruction::kInstrSize; | 583 cur += Instruction::kInstrSize; |
567 } | 584 } |
568 } else if (strcmp(cmd, "gdb") == 0) { | 585 } else if (strcmp(cmd, "gdb") == 0) { |
569 PrintF("relinquishing control to gdb\n"); | 586 PrintF("relinquishing control to gdb\n"); |
570 v8::base::OS::DebugBreak(); | 587 v8::base::OS::DebugBreak(); |
571 PrintF("regaining control from gdb\n"); | 588 PrintF("regaining control from gdb\n"); |
572 } else if (strcmp(cmd, "break") == 0) { | 589 } else if (strcmp(cmd, "break") == 0) { |
573 if (argc == 2) { | 590 if (argc == 2) { |
574 int32_t value; | 591 int64_t value; |
575 if (GetValue(arg1, &value)) { | 592 if (GetValue(arg1, &value)) { |
576 if (!SetBreakpoint(reinterpret_cast<Instruction*>(value))) { | 593 if (!SetBreakpoint(reinterpret_cast<Instruction*>(value))) { |
577 PrintF("setting breakpoint failed\n"); | 594 PrintF("setting breakpoint failed\n"); |
578 } | 595 } |
579 } else { | 596 } else { |
580 PrintF("%s unrecognized\n", arg1); | 597 PrintF("%s unrecognized\n", arg1); |
581 } | 598 } |
582 } else { | 599 } else { |
583 PrintF("break <address>\n"); | 600 PrintF("break <address>\n"); |
584 } | 601 } |
585 } else if (strcmp(cmd, "del") == 0) { | 602 } else if (strcmp(cmd, "del") == 0) { |
586 if (!DeleteBreakpoint(NULL)) { | 603 if (!DeleteBreakpoint(NULL)) { |
587 PrintF("deleting breakpoint failed\n"); | 604 PrintF("deleting breakpoint failed\n"); |
588 } | 605 } |
589 } else if (strcmp(cmd, "flags") == 0) { | 606 } else if (strcmp(cmd, "flags") == 0) { |
590 PrintF("No flags on MIPS !\n"); | 607 PrintF("No flags on MIPS !\n"); |
591 } else if (strcmp(cmd, "stop") == 0) { | 608 } else if (strcmp(cmd, "stop") == 0) { |
592 int32_t value; | 609 int64_t value; |
593 intptr_t stop_pc = sim_->get_pc() - | 610 intptr_t stop_pc = sim_->get_pc() - |
594 2 * Instruction::kInstrSize; | 611 2 * Instruction::kInstrSize; |
595 Instruction* stop_instr = reinterpret_cast<Instruction*>(stop_pc); | 612 Instruction* stop_instr = reinterpret_cast<Instruction*>(stop_pc); |
596 Instruction* msg_address = | 613 Instruction* msg_address = |
597 reinterpret_cast<Instruction*>(stop_pc + | 614 reinterpret_cast<Instruction*>(stop_pc + |
598 Instruction::kInstrSize); | 615 Instruction::kInstrSize); |
599 if ((argc == 2) && (strcmp(arg1, "unstop") == 0)) { | 616 if ((argc == 2) && (strcmp(arg1, "unstop") == 0)) { |
600 // Remove the current stop. | 617 // Remove the current stop. |
601 if (sim_->IsStopInstruction(stop_instr)) { | 618 if (sim_->IsStopInstruction(stop_instr)) { |
602 stop_instr->SetInstructionBits(kNopInstr); | 619 stop_instr->SetInstructionBits(kNopInstr); |
(...skipping 56 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
659 // Use a reasonably large buffer. | 676 // Use a reasonably large buffer. |
660 v8::internal::EmbeddedVector<char, 256> buffer; | 677 v8::internal::EmbeddedVector<char, 256> buffer; |
661 | 678 |
662 byte* cur = NULL; | 679 byte* cur = NULL; |
663 byte* end = NULL; | 680 byte* end = NULL; |
664 | 681 |
665 if (argc == 1) { | 682 if (argc == 1) { |
666 cur = reinterpret_cast<byte*>(sim_->get_pc()); | 683 cur = reinterpret_cast<byte*>(sim_->get_pc()); |
667 end = cur + (10 * Instruction::kInstrSize); | 684 end = cur + (10 * Instruction::kInstrSize); |
668 } else if (argc == 2) { | 685 } else if (argc == 2) { |
669 int32_t value; | 686 int64_t value; |
670 if (GetValue(arg1, &value)) { | 687 if (GetValue(arg1, &value)) { |
671 cur = reinterpret_cast<byte*>(value); | 688 cur = reinterpret_cast<byte*>(value); |
672 // no length parameter passed, assume 10 instructions | 689 // no length parameter passed, assume 10 instructions |
673 end = cur + (10 * Instruction::kInstrSize); | 690 end = cur + (10 * Instruction::kInstrSize); |
674 } | 691 } |
675 } else { | 692 } else { |
676 int32_t value1; | 693 int64_t value1; |
677 int32_t value2; | 694 int64_t value2; |
678 if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) { | 695 if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) { |
679 cur = reinterpret_cast<byte*>(value1); | 696 cur = reinterpret_cast<byte*>(value1); |
680 end = cur + (value2 * Instruction::kInstrSize); | 697 end = cur + (value2 * Instruction::kInstrSize); |
681 } | 698 } |
682 } | 699 } |
683 | 700 |
684 while (cur < end) { | 701 while (cur < end) { |
685 dasm.InstructionDecode(buffer, cur); | 702 dasm.InstructionDecode(buffer, cur); |
686 PrintF(" 0x%08x %s\n", | 703 PrintF(" 0x%08lx %s\n", |
687 reinterpret_cast<intptr_t>(cur), buffer.start()); | 704 reinterpret_cast<intptr_t>(cur), buffer.start()); |
688 cur += Instruction::kInstrSize; | 705 cur += Instruction::kInstrSize; |
689 } | 706 } |
690 } else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) { | 707 } else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) { |
691 PrintF("cont\n"); | 708 PrintF("cont\n"); |
692 PrintF(" continue execution (alias 'c')\n"); | 709 PrintF(" continue execution (alias 'c')\n"); |
693 PrintF("stepi\n"); | 710 PrintF("stepi\n"); |
694 PrintF(" step one instruction (alias 'si')\n"); | 711 PrintF(" step one instruction (alias 'si')\n"); |
695 PrintF("print <register>\n"); | 712 PrintF("print <register>\n"); |
696 PrintF(" print register content (alias 'p')\n"); | 713 PrintF(" print register content (alias 'p')\n"); |
(...skipping 76 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
773 | 790 |
774 void Simulator::set_last_debugger_input(char* input) { | 791 void Simulator::set_last_debugger_input(char* input) { |
775 DeleteArray(last_debugger_input_); | 792 DeleteArray(last_debugger_input_); |
776 last_debugger_input_ = input; | 793 last_debugger_input_ = input; |
777 } | 794 } |
778 | 795 |
779 | 796 |
780 void Simulator::FlushICache(v8::internal::HashMap* i_cache, | 797 void Simulator::FlushICache(v8::internal::HashMap* i_cache, |
781 void* start_addr, | 798 void* start_addr, |
782 size_t size) { | 799 size_t size) { |
783 intptr_t start = reinterpret_cast<intptr_t>(start_addr); | 800 int64_t start = reinterpret_cast<int64_t>(start_addr); |
784 int intra_line = (start & CachePage::kLineMask); | 801 int64_t intra_line = (start & CachePage::kLineMask); |
785 start -= intra_line; | 802 start -= intra_line; |
786 size += intra_line; | 803 size += intra_line; |
787 size = ((size - 1) | CachePage::kLineMask) + 1; | 804 size = ((size - 1) | CachePage::kLineMask) + 1; |
788 int offset = (start & CachePage::kPageMask); | 805 int offset = (start & CachePage::kPageMask); |
789 while (!AllOnOnePage(start, size - 1)) { | 806 while (!AllOnOnePage(start, size - 1)) { |
790 int bytes_to_flush = CachePage::kPageSize - offset; | 807 int bytes_to_flush = CachePage::kPageSize - offset; |
791 FlushOnePage(i_cache, start, bytes_to_flush); | 808 FlushOnePage(i_cache, start, bytes_to_flush); |
792 start += bytes_to_flush; | 809 start += bytes_to_flush; |
793 size -= bytes_to_flush; | 810 size -= bytes_to_flush; |
794 ASSERT_EQ(0, start & CachePage::kPageMask); | 811 ASSERT_EQ((uint64_t)0, start & CachePage::kPageMask); |
795 offset = 0; | 812 offset = 0; |
796 } | 813 } |
797 if (size != 0) { | 814 if (size != 0) { |
798 FlushOnePage(i_cache, start, size); | 815 FlushOnePage(i_cache, start, size); |
799 } | 816 } |
800 } | 817 } |
801 | 818 |
802 | 819 |
803 CachePage* Simulator::GetCachePage(v8::internal::HashMap* i_cache, void* page) { | 820 CachePage* Simulator::GetCachePage(v8::internal::HashMap* i_cache, void* page) { |
804 v8::internal::HashMap::Entry* entry = i_cache->Lookup(page, | 821 v8::internal::HashMap::Entry* entry = i_cache->Lookup(page, |
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823 void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask)); | 840 void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask)); |
824 int offset = (start & CachePage::kPageMask); | 841 int offset = (start & CachePage::kPageMask); |
825 CachePage* cache_page = GetCachePage(i_cache, page); | 842 CachePage* cache_page = GetCachePage(i_cache, page); |
826 char* valid_bytemap = cache_page->ValidityByte(offset); | 843 char* valid_bytemap = cache_page->ValidityByte(offset); |
827 memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift); | 844 memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift); |
828 } | 845 } |
829 | 846 |
830 | 847 |
831 void Simulator::CheckICache(v8::internal::HashMap* i_cache, | 848 void Simulator::CheckICache(v8::internal::HashMap* i_cache, |
832 Instruction* instr) { | 849 Instruction* instr) { |
833 intptr_t address = reinterpret_cast<intptr_t>(instr); | 850 int64_t address = reinterpret_cast<int64_t>(instr); |
834 void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask)); | 851 void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask)); |
835 void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask)); | 852 void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask)); |
836 int offset = (address & CachePage::kPageMask); | 853 int offset = (address & CachePage::kPageMask); |
837 CachePage* cache_page = GetCachePage(i_cache, page); | 854 CachePage* cache_page = GetCachePage(i_cache, page); |
838 char* cache_valid_byte = cache_page->ValidityByte(offset); | 855 char* cache_valid_byte = cache_page->ValidityByte(offset); |
839 bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID); | 856 bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID); |
840 char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask); | 857 char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask); |
841 if (cache_hit) { | 858 if (cache_hit) { |
842 // Check that the data in memory matches the contents of the I-cache. | 859 // Check that the data in memory matches the contents of the I-cache. |
843 CHECK_EQ(0, memcmp(reinterpret_cast<void*>(instr), | 860 CHECK_EQ(0, memcmp(reinterpret_cast<void*>(instr), |
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861 | 878 |
862 Simulator::Simulator(Isolate* isolate) : isolate_(isolate) { | 879 Simulator::Simulator(Isolate* isolate) : isolate_(isolate) { |
863 i_cache_ = isolate_->simulator_i_cache(); | 880 i_cache_ = isolate_->simulator_i_cache(); |
864 if (i_cache_ == NULL) { | 881 if (i_cache_ == NULL) { |
865 i_cache_ = new v8::internal::HashMap(&ICacheMatch); | 882 i_cache_ = new v8::internal::HashMap(&ICacheMatch); |
866 isolate_->set_simulator_i_cache(i_cache_); | 883 isolate_->set_simulator_i_cache(i_cache_); |
867 } | 884 } |
868 Initialize(isolate); | 885 Initialize(isolate); |
869 // Set up simulator support first. Some of this information is needed to | 886 // Set up simulator support first. Some of this information is needed to |
870 // setup the architecture state. | 887 // setup the architecture state. |
| 888 stack_size_ = FLAG_sim_stack_size * KB; |
871 stack_ = reinterpret_cast<char*>(malloc(stack_size_)); | 889 stack_ = reinterpret_cast<char*>(malloc(stack_size_)); |
872 pc_modified_ = false; | 890 pc_modified_ = false; |
873 icount_ = 0; | 891 icount_ = 0; |
874 break_count_ = 0; | 892 break_count_ = 0; |
875 break_pc_ = NULL; | 893 break_pc_ = NULL; |
876 break_instr_ = 0; | 894 break_instr_ = 0; |
877 | 895 |
878 // Set up architecture state. | 896 // Set up architecture state. |
879 // All registers are initialized to zero to start with. | 897 // All registers are initialized to zero to start with. |
880 for (int i = 0; i < kNumSimuRegisters; i++) { | 898 for (int i = 0; i < kNumSimuRegisters; i++) { |
881 registers_[i] = 0; | 899 registers_[i] = 0; |
882 } | 900 } |
883 for (int i = 0; i < kNumFPURegisters; i++) { | 901 for (int i = 0; i < kNumFPURegisters; i++) { |
884 FPUregisters_[i] = 0; | 902 FPUregisters_[i] = 0; |
885 } | 903 } |
886 FCSR_ = 0; | 904 FCSR_ = 0; |
887 | 905 |
888 // The sp is initialized to point to the bottom (high address) of the | 906 // The sp is initialized to point to the bottom (high address) of the |
889 // allocated stack area. To be safe in potential stack underflows we leave | 907 // allocated stack area. To be safe in potential stack underflows we leave |
890 // some buffer below. | 908 // some buffer below. |
891 registers_[sp] = reinterpret_cast<int32_t>(stack_) + stack_size_ - 64; | 909 registers_[sp] = reinterpret_cast<int64_t>(stack_) + stack_size_ - 64; |
892 // The ra and pc are initialized to a known bad value that will cause an | 910 // The ra and pc are initialized to a known bad value that will cause an |
893 // access violation if the simulator ever tries to execute it. | 911 // access violation if the simulator ever tries to execute it. |
894 registers_[pc] = bad_ra; | 912 registers_[pc] = bad_ra; |
895 registers_[ra] = bad_ra; | 913 registers_[ra] = bad_ra; |
896 InitializeCoverage(); | 914 InitializeCoverage(); |
897 for (int i = 0; i < kNumExceptions; i++) { | 915 for (int i = 0; i < kNumExceptions; i++) { |
898 exceptions[i] = 0; | 916 exceptions[i] = 0; |
899 } | 917 } |
900 | 918 |
901 last_debugger_input_ = NULL; | 919 last_debugger_input_ = NULL; |
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946 return new Redirection(external_function, type); | 964 return new Redirection(external_function, type); |
947 } | 965 } |
948 | 966 |
949 static Redirection* FromSwiInstruction(Instruction* swi_instruction) { | 967 static Redirection* FromSwiInstruction(Instruction* swi_instruction) { |
950 char* addr_of_swi = reinterpret_cast<char*>(swi_instruction); | 968 char* addr_of_swi = reinterpret_cast<char*>(swi_instruction); |
951 char* addr_of_redirection = | 969 char* addr_of_redirection = |
952 addr_of_swi - OFFSET_OF(Redirection, swi_instruction_); | 970 addr_of_swi - OFFSET_OF(Redirection, swi_instruction_); |
953 return reinterpret_cast<Redirection*>(addr_of_redirection); | 971 return reinterpret_cast<Redirection*>(addr_of_redirection); |
954 } | 972 } |
955 | 973 |
956 static void* ReverseRedirection(int32_t reg) { | 974 static void* ReverseRedirection(int64_t reg) { |
957 Redirection* redirection = FromSwiInstruction( | 975 Redirection* redirection = FromSwiInstruction( |
958 reinterpret_cast<Instruction*>(reinterpret_cast<void*>(reg))); | 976 reinterpret_cast<Instruction*>(reinterpret_cast<void*>(reg))); |
959 return redirection->external_function(); | 977 return redirection->external_function(); |
960 } | 978 } |
961 | 979 |
962 private: | 980 private: |
963 void* external_function_; | 981 void* external_function_; |
964 uint32_t swi_instruction_; | 982 uint32_t swi_instruction_; |
965 ExternalReference::Type type_; | 983 ExternalReference::Type type_; |
966 Redirection* next_; | 984 Redirection* next_; |
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986 // TODO(146): delete the simulator object when a thread/isolate goes away. | 1004 // TODO(146): delete the simulator object when a thread/isolate goes away. |
987 sim = new Simulator(isolate); | 1005 sim = new Simulator(isolate); |
988 isolate_data->set_simulator(sim); | 1006 isolate_data->set_simulator(sim); |
989 } | 1007 } |
990 return sim; | 1008 return sim; |
991 } | 1009 } |
992 | 1010 |
993 | 1011 |
994 // Sets the register in the architecture state. It will also deal with updating | 1012 // Sets the register in the architecture state. It will also deal with updating |
995 // Simulator internal state for special registers such as PC. | 1013 // Simulator internal state for special registers such as PC. |
996 void Simulator::set_register(int reg, int32_t value) { | 1014 void Simulator::set_register(int reg, int64_t value) { |
997 ASSERT((reg >= 0) && (reg < kNumSimuRegisters)); | 1015 ASSERT((reg >= 0) && (reg < kNumSimuRegisters)); |
998 if (reg == pc) { | 1016 if (reg == pc) { |
999 pc_modified_ = true; | 1017 pc_modified_ = true; |
1000 } | 1018 } |
1001 | 1019 |
1002 // Zero register always holds 0. | 1020 // Zero register always holds 0. |
1003 registers_[reg] = (reg == 0) ? 0 : value; | 1021 registers_[reg] = (reg == 0) ? 0 : value; |
1004 } | 1022 } |
1005 | 1023 |
1006 | 1024 |
1007 void Simulator::set_dw_register(int reg, const int* dbl) { | 1025 void Simulator::set_dw_register(int reg, const int* dbl) { |
1008 ASSERT((reg >= 0) && (reg < kNumSimuRegisters)); | 1026 ASSERT((reg >= 0) && (reg < kNumSimuRegisters)); |
1009 registers_[reg] = dbl[0]; | 1027 registers_[reg] = dbl[1]; |
1010 registers_[reg + 1] = dbl[1]; | 1028 registers_[reg] = registers_[reg] << 32; |
| 1029 registers_[reg] += dbl[0]; |
1011 } | 1030 } |
1012 | 1031 |
1013 | 1032 |
1014 void Simulator::set_fpu_register(int fpureg, int32_t value) { | 1033 void Simulator::set_fpu_register(int fpureg, int64_t value) { |
1015 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 1034 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1016 FPUregisters_[fpureg] = value; | 1035 FPUregisters_[fpureg] = value; |
1017 } | 1036 } |
1018 | 1037 |
1019 | 1038 |
| 1039 void Simulator::set_fpu_register_word(int fpureg, int32_t value) { |
| 1040 // Set ONLY lower 32-bits, leaving upper bits untouched. |
| 1041 // TODO(plind): big endian issue. |
| 1042 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
| 1043 int32_t *pword = reinterpret_cast<int32_t*>(&FPUregisters_[fpureg]); |
| 1044 *pword = value; |
| 1045 } |
| 1046 |
| 1047 |
| 1048 void Simulator::set_fpu_register_hi_word(int fpureg, int32_t value) { |
| 1049 // Set ONLY upper 32-bits, leaving lower bits untouched. |
| 1050 // TODO(plind): big endian issue. |
| 1051 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
| 1052 int32_t *phiword = (reinterpret_cast<int32_t*>(&FPUregisters_[fpureg])) + 1; |
| 1053 *phiword = value; |
| 1054 } |
| 1055 |
| 1056 |
1020 void Simulator::set_fpu_register_float(int fpureg, float value) { | 1057 void Simulator::set_fpu_register_float(int fpureg, float value) { |
1021 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 1058 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1022 *BitCast<float*>(&FPUregisters_[fpureg]) = value; | 1059 *BitCast<float*>(&FPUregisters_[fpureg]) = value; |
1023 } | 1060 } |
1024 | 1061 |
1025 | 1062 |
1026 void Simulator::set_fpu_register_double(int fpureg, double value) { | 1063 void Simulator::set_fpu_register_double(int fpureg, double value) { |
1027 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); | 1064 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1028 *BitCast<double*>(&FPUregisters_[fpureg]) = value; | 1065 *BitCast<double*>(&FPUregisters_[fpureg]) = value; |
1029 } | 1066 } |
1030 | 1067 |
1031 | 1068 |
1032 // Get the register from the architecture state. This function does handle | 1069 // Get the register from the architecture state. This function does handle |
1033 // the special case of accessing the PC register. | 1070 // the special case of accessing the PC register. |
1034 int32_t Simulator::get_register(int reg) const { | 1071 int64_t Simulator::get_register(int reg) const { |
1035 ASSERT((reg >= 0) && (reg < kNumSimuRegisters)); | 1072 ASSERT((reg >= 0) && (reg < kNumSimuRegisters)); |
1036 if (reg == 0) | 1073 if (reg == 0) |
1037 return 0; | 1074 return 0; |
1038 else | 1075 else |
1039 return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0); | 1076 return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0); |
1040 } | 1077 } |
1041 | 1078 |
1042 | 1079 |
1043 double Simulator::get_double_from_register_pair(int reg) { | 1080 double Simulator::get_double_from_register_pair(int reg) { |
| 1081 // TODO(plind): bad ABI stuff, refactor or remove. |
1044 ASSERT((reg >= 0) && (reg < kNumSimuRegisters) && ((reg % 2) == 0)); | 1082 ASSERT((reg >= 0) && (reg < kNumSimuRegisters) && ((reg % 2) == 0)); |
1045 | 1083 |
1046 double dm_val = 0.0; | 1084 double dm_val = 0.0; |
1047 // Read the bits from the unsigned integer register_[] array | 1085 // Read the bits from the unsigned integer register_[] array |
1048 // into the double precision floating point value and return it. | 1086 // into the double precision floating point value and return it. |
1049 char buffer[2 * sizeof(registers_[0])]; | 1087 char buffer[sizeof(registers_[0])]; |
1050 memcpy(buffer, ®isters_[reg], 2 * sizeof(registers_[0])); | 1088 memcpy(buffer, ®isters_[reg], sizeof(registers_[0])); |
1051 memcpy(&dm_val, buffer, 2 * sizeof(registers_[0])); | 1089 memcpy(&dm_val, buffer, sizeof(registers_[0])); |
1052 return(dm_val); | 1090 return(dm_val); |
1053 } | 1091 } |
1054 | 1092 |
1055 | 1093 |
1056 int32_t Simulator::get_fpu_register(int fpureg) const { | 1094 int64_t Simulator::get_fpu_register(int fpureg) const { |
1057 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 1095 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1058 return FPUregisters_[fpureg]; | 1096 return FPUregisters_[fpureg]; |
1059 } | 1097 } |
1060 | 1098 |
1061 | 1099 |
1062 int64_t Simulator::get_fpu_register_long(int fpureg) const { | 1100 int32_t Simulator::get_fpu_register_word(int fpureg) const { |
1063 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); | 1101 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1064 return *BitCast<int64_t*>( | 1102 return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff); |
1065 const_cast<int32_t*>(&FPUregisters_[fpureg])); | 1103 } |
| 1104 |
| 1105 |
| 1106 int32_t Simulator::get_fpu_register_signed_word(int fpureg) const { |
| 1107 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
| 1108 return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff); |
| 1109 } |
| 1110 |
| 1111 |
| 1112 uint32_t Simulator::get_fpu_register_hi_word(int fpureg) const { |
| 1113 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
| 1114 return static_cast<uint32_t>((FPUregisters_[fpureg] >> 32) & 0xffffffff); |
1066 } | 1115 } |
1067 | 1116 |
1068 | 1117 |
1069 float Simulator::get_fpu_register_float(int fpureg) const { | 1118 float Simulator::get_fpu_register_float(int fpureg) const { |
1070 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 1119 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1071 return *BitCast<float*>( | 1120 return *BitCast<float*>( |
1072 const_cast<int32_t*>(&FPUregisters_[fpureg])); | 1121 const_cast<int64_t*>(&FPUregisters_[fpureg])); |
1073 } | 1122 } |
1074 | 1123 |
1075 | 1124 |
1076 double Simulator::get_fpu_register_double(int fpureg) const { | 1125 double Simulator::get_fpu_register_double(int fpureg) const { |
1077 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); | 1126 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1078 return *BitCast<double*>(const_cast<int32_t*>(&FPUregisters_[fpureg])); | 1127 return *BitCast<double*>(&FPUregisters_[fpureg]); |
1079 } | 1128 } |
1080 | 1129 |
1081 | 1130 |
1082 // Runtime FP routines take up to two double arguments and zero | 1131 // Runtime FP routines take up to two double arguments and zero |
1083 // or one integer arguments. All are constructed here, | 1132 // or one integer arguments. All are constructed here, |
1084 // from a0-a3 or f12 and f14. | 1133 // from a0-a3 or f12 and f13 (n64), or f14 (O32). |
1085 void Simulator::GetFpArgs(double* x, double* y, int32_t* z) { | 1134 void Simulator::GetFpArgs(double* x, double* y, int32_t* z) { |
1086 if (!IsMipsSoftFloatABI) { | 1135 if (!IsMipsSoftFloatABI) { |
| 1136 const int fparg2 = (kMipsAbi == kN64) ? 13 : 14; |
1087 *x = get_fpu_register_double(12); | 1137 *x = get_fpu_register_double(12); |
1088 *y = get_fpu_register_double(14); | 1138 *y = get_fpu_register_double(fparg2); |
1089 *z = get_register(a2); | 1139 *z = get_register(a2); |
1090 } else { | 1140 } else { |
| 1141 // TODO(plind): bad ABI stuff, refactor or remove. |
1091 // We use a char buffer to get around the strict-aliasing rules which | 1142 // We use a char buffer to get around the strict-aliasing rules which |
1092 // otherwise allow the compiler to optimize away the copy. | 1143 // otherwise allow the compiler to optimize away the copy. |
1093 char buffer[sizeof(*x)]; | 1144 char buffer[sizeof(*x)]; |
1094 int32_t* reg_buffer = reinterpret_cast<int32_t*>(buffer); | 1145 int32_t* reg_buffer = reinterpret_cast<int32_t*>(buffer); |
1095 | 1146 |
1096 // Registers a0 and a1 -> x. | 1147 // Registers a0 and a1 -> x. |
1097 reg_buffer[0] = get_register(a0); | 1148 reg_buffer[0] = get_register(a0); |
1098 reg_buffer[1] = get_register(a1); | 1149 reg_buffer[1] = get_register(a1); |
1099 memcpy(x, buffer, sizeof(buffer)); | 1150 memcpy(x, buffer, sizeof(buffer)); |
1100 // Registers a2 and a3 -> y. | 1151 // Registers a2 and a3 -> y. |
1101 reg_buffer[0] = get_register(a2); | 1152 reg_buffer[0] = get_register(a2); |
1102 reg_buffer[1] = get_register(a3); | 1153 reg_buffer[1] = get_register(a3); |
1103 memcpy(y, buffer, sizeof(buffer)); | 1154 memcpy(y, buffer, sizeof(buffer)); |
1104 // Register 2 -> z. | 1155 // Register 2 -> z. |
1105 reg_buffer[0] = get_register(a2); | 1156 reg_buffer[0] = get_register(a2); |
1106 memcpy(z, buffer, sizeof(*z)); | 1157 memcpy(z, buffer, sizeof(*z)); |
1107 } | 1158 } |
1108 } | 1159 } |
1109 | 1160 |
1110 | 1161 |
1111 // The return value is either in v0/v1 or f0. | 1162 // The return value is either in v0/v1 or f0. |
1112 void Simulator::SetFpResult(const double& result) { | 1163 void Simulator::SetFpResult(const double& result) { |
1113 if (!IsMipsSoftFloatABI) { | 1164 if (!IsMipsSoftFloatABI) { |
1114 set_fpu_register_double(0, result); | 1165 set_fpu_register_double(0, result); |
1115 } else { | 1166 } else { |
1116 char buffer[2 * sizeof(registers_[0])]; | 1167 char buffer[2 * sizeof(registers_[0])]; |
1117 int32_t* reg_buffer = reinterpret_cast<int32_t*>(buffer); | 1168 int64_t* reg_buffer = reinterpret_cast<int64_t*>(buffer); |
1118 memcpy(buffer, &result, sizeof(buffer)); | 1169 memcpy(buffer, &result, sizeof(buffer)); |
1119 // Copy result to v0 and v1. | 1170 // Copy result to v0 and v1. |
1120 set_register(v0, reg_buffer[0]); | 1171 set_register(v0, reg_buffer[0]); |
1121 set_register(v1, reg_buffer[1]); | 1172 set_register(v1, reg_buffer[1]); |
1122 } | 1173 } |
1123 } | 1174 } |
1124 | 1175 |
1125 | 1176 |
1126 // Helper functions for setting and testing the FCSR register's bits. | 1177 // Helper functions for setting and testing the FCSR register's bits. |
1127 void Simulator::set_fcsr_bit(uint32_t cc, bool value) { | 1178 void Simulator::set_fcsr_bit(uint32_t cc, bool value) { |
1128 if (value) { | 1179 if (value) { |
1129 FCSR_ |= (1 << cc); | 1180 FCSR_ |= (1 << cc); |
1130 } else { | 1181 } else { |
1131 FCSR_ &= ~(1 << cc); | 1182 FCSR_ &= ~(1 << cc); |
1132 } | 1183 } |
1133 } | 1184 } |
1134 | 1185 |
1135 | 1186 |
1136 bool Simulator::test_fcsr_bit(uint32_t cc) { | 1187 bool Simulator::test_fcsr_bit(uint32_t cc) { |
1137 return FCSR_ & (1 << cc); | 1188 return FCSR_ & (1 << cc); |
1138 } | 1189 } |
1139 | 1190 |
1140 | 1191 |
1141 // Sets the rounding error codes in FCSR based on the result of the rounding. | 1192 // Sets the rounding error codes in FCSR based on the result of the rounding. |
1142 // Returns true if the operation was invalid. | 1193 // Returns true if the operation was invalid. |
1143 bool Simulator::set_fcsr_round_error(double original, double rounded) { | 1194 bool Simulator::set_fcsr_round_error(double original, double rounded) { |
1144 bool ret = false; | 1195 bool ret = false; |
| 1196 double max_int32 = std::numeric_limits<int32_t>::max(); |
| 1197 double min_int32 = std::numeric_limits<int32_t>::min(); |
1145 | 1198 |
1146 if (!std::isfinite(original) || !std::isfinite(rounded)) { | 1199 if (!std::isfinite(original) || !std::isfinite(rounded)) { |
1147 set_fcsr_bit(kFCSRInvalidOpFlagBit, true); | 1200 set_fcsr_bit(kFCSRInvalidOpFlagBit, true); |
| 1201 ret = true; |
| 1202 } |
| 1203 |
| 1204 if (original != rounded) { |
| 1205 set_fcsr_bit(kFCSRInexactFlagBit, true); |
| 1206 } |
| 1207 |
| 1208 if (rounded < DBL_MIN && rounded > -DBL_MIN && rounded != 0) { |
| 1209 set_fcsr_bit(kFCSRUnderflowFlagBit, true); |
| 1210 ret = true; |
| 1211 } |
| 1212 |
| 1213 if (rounded > max_int32 || rounded < min_int32) { |
| 1214 set_fcsr_bit(kFCSROverflowFlagBit, true); |
| 1215 // The reference is not really clear but it seems this is required: |
| 1216 set_fcsr_bit(kFCSRInvalidOpFlagBit, true); |
| 1217 ret = true; |
| 1218 } |
| 1219 |
| 1220 return ret; |
| 1221 } |
| 1222 |
| 1223 |
| 1224 // Sets the rounding error codes in FCSR based on the result of the rounding. |
| 1225 // Returns true if the operation was invalid. |
| 1226 bool Simulator::set_fcsr_round64_error(double original, double rounded) { |
| 1227 bool ret = false; |
| 1228 double max_int64 = std::numeric_limits<int64_t>::max(); |
| 1229 double min_int64 = std::numeric_limits<int64_t>::min(); |
| 1230 |
| 1231 if (!std::isfinite(original) || !std::isfinite(rounded)) { |
| 1232 set_fcsr_bit(kFCSRInvalidOpFlagBit, true); |
1148 ret = true; | 1233 ret = true; |
1149 } | 1234 } |
1150 | 1235 |
1151 if (original != rounded) { | 1236 if (original != rounded) { |
1152 set_fcsr_bit(kFCSRInexactFlagBit, true); | 1237 set_fcsr_bit(kFCSRInexactFlagBit, true); |
1153 } | 1238 } |
1154 | 1239 |
1155 if (rounded < DBL_MIN && rounded > -DBL_MIN && rounded != 0) { | 1240 if (rounded < DBL_MIN && rounded > -DBL_MIN && rounded != 0) { |
1156 set_fcsr_bit(kFCSRUnderflowFlagBit, true); | 1241 set_fcsr_bit(kFCSRUnderflowFlagBit, true); |
1157 ret = true; | 1242 ret = true; |
1158 } | 1243 } |
1159 | 1244 |
1160 if (rounded > INT_MAX || rounded < INT_MIN) { | 1245 if (rounded > max_int64 || rounded < min_int64) { |
1161 set_fcsr_bit(kFCSROverflowFlagBit, true); | 1246 set_fcsr_bit(kFCSROverflowFlagBit, true); |
1162 // The reference is not really clear but it seems this is required: | 1247 // The reference is not really clear but it seems this is required: |
1163 set_fcsr_bit(kFCSRInvalidOpFlagBit, true); | 1248 set_fcsr_bit(kFCSRInvalidOpFlagBit, true); |
1164 ret = true; | 1249 ret = true; |
1165 } | 1250 } |
1166 | 1251 |
1167 return ret; | 1252 return ret; |
1168 } | 1253 } |
1169 | 1254 |
1170 | 1255 |
1171 // Raw access to the PC register. | 1256 // Raw access to the PC register. |
1172 void Simulator::set_pc(int32_t value) { | 1257 void Simulator::set_pc(int64_t value) { |
1173 pc_modified_ = true; | 1258 pc_modified_ = true; |
1174 registers_[pc] = value; | 1259 registers_[pc] = value; |
1175 } | 1260 } |
1176 | 1261 |
1177 | 1262 |
1178 bool Simulator::has_bad_pc() const { | 1263 bool Simulator::has_bad_pc() const { |
1179 return ((registers_[pc] == bad_ra) || (registers_[pc] == end_sim_pc)); | 1264 return ((registers_[pc] == bad_ra) || (registers_[pc] == end_sim_pc)); |
1180 } | 1265 } |
1181 | 1266 |
1182 | 1267 |
1183 // Raw access to the PC register without the special adjustment when reading. | 1268 // Raw access to the PC register without the special adjustment when reading. |
1184 int32_t Simulator::get_pc() const { | 1269 int64_t Simulator::get_pc() const { |
1185 return registers_[pc]; | 1270 return registers_[pc]; |
1186 } | 1271 } |
1187 | 1272 |
1188 | 1273 |
1189 // The MIPS cannot do unaligned reads and writes. On some MIPS platforms an | 1274 // The MIPS cannot do unaligned reads and writes. On some MIPS platforms an |
1190 // interrupt is caused. On others it does a funky rotation thing. For now we | 1275 // interrupt is caused. On others it does a funky rotation thing. For now we |
1191 // simply disallow unaligned reads, but at some point we may want to move to | 1276 // simply disallow unaligned reads, but at some point we may want to move to |
1192 // emulating the rotate behaviour. Note that simulator runs have the runtime | 1277 // emulating the rotate behaviour. Note that simulator runs have the runtime |
1193 // system running directly on the host system and only generated code is | 1278 // system running directly on the host system and only generated code is |
1194 // executed in the simulator. Since the host is typically IA32 we will not | 1279 // executed in the simulator. Since the host is typically IA32 we will not |
1195 // get the correct MIPS-like behaviour on unaligned accesses. | 1280 // get the correct MIPS-like behaviour on unaligned accesses. |
1196 | 1281 |
1197 int Simulator::ReadW(int32_t addr, Instruction* instr) { | 1282 // TODO(plind): refactor this messy debug code when we do unaligned access. |
| 1283 void Simulator::DieOrDebug() { |
| 1284 if (1) { // Flag for this was removed. |
| 1285 MipsDebugger dbg(this); |
| 1286 dbg.Debug(); |
| 1287 } else { |
| 1288 base::OS::Abort(); |
| 1289 } |
| 1290 } |
| 1291 |
| 1292 |
| 1293 void Simulator::TraceRegWr(int64_t value) { |
| 1294 if (::v8::internal::FLAG_trace_sim) { |
| 1295 SNPrintF(trace_buf_, "%016lx", value); |
| 1296 } |
| 1297 } |
| 1298 |
| 1299 |
| 1300 // TODO(plind): consider making icount_ printing a flag option. |
| 1301 void Simulator::TraceMemRd(int64_t addr, int64_t value) { |
| 1302 if (::v8::internal::FLAG_trace_sim) { |
| 1303 SNPrintF(trace_buf_, "%016lx <-- [%016lx] (%ld)", |
| 1304 value, addr, icount_); |
| 1305 } |
| 1306 } |
| 1307 |
| 1308 |
| 1309 void Simulator::TraceMemWr(int64_t addr, int64_t value, TraceType t) { |
| 1310 if (::v8::internal::FLAG_trace_sim) { |
| 1311 switch (t) { |
| 1312 case BYTE: |
| 1313 SNPrintF(trace_buf_, " %02x --> [%016lx]", |
| 1314 static_cast<int8_t>(value), addr); |
| 1315 break; |
| 1316 case HALF: |
| 1317 SNPrintF(trace_buf_, " %04x --> [%016lx]", |
| 1318 static_cast<int16_t>(value), addr); |
| 1319 break; |
| 1320 case WORD: |
| 1321 SNPrintF(trace_buf_, " %08x --> [%016lx]", |
| 1322 static_cast<int32_t>(value), addr); |
| 1323 break; |
| 1324 case DWORD: |
| 1325 SNPrintF(trace_buf_, "%016lx --> [%016lx] (%ld)", |
| 1326 value, addr, icount_); |
| 1327 break; |
| 1328 } |
| 1329 } |
| 1330 } |
| 1331 |
| 1332 |
| 1333 // TODO(plind): sign-extend and zero-extend not implmented properly |
| 1334 // on all the ReadXX functions, I don't think re-interpret cast does it. |
| 1335 int32_t Simulator::ReadW(int64_t addr, Instruction* instr) { |
1198 if (addr >=0 && addr < 0x400) { | 1336 if (addr >=0 && addr < 0x400) { |
1199 // This has to be a NULL-dereference, drop into debugger. | 1337 // This has to be a NULL-dereference, drop into debugger. |
1200 PrintF("Memory read from bad address: 0x%08x, pc=0x%08x\n", | 1338 PrintF("Memory read from bad address: 0x%08lx, pc=0x%08lx\n", |
1201 addr, reinterpret_cast<intptr_t>(instr)); | 1339 addr, reinterpret_cast<intptr_t>(instr)); |
1202 MipsDebugger dbg(this); | 1340 DieOrDebug(); |
1203 dbg.Debug(); | |
1204 } | 1341 } |
1205 if ((addr & kPointerAlignmentMask) == 0) { | 1342 if ((addr & 0x3) == 0) { |
1206 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); | 1343 int32_t* ptr = reinterpret_cast<int32_t*>(addr); |
| 1344 TraceMemRd(addr, static_cast<int64_t>(*ptr)); |
1207 return *ptr; | 1345 return *ptr; |
1208 } | 1346 } |
1209 PrintF("Unaligned read at 0x%08x, pc=0x%08" V8PRIxPTR "\n", | 1347 PrintF("Unaligned read at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
1210 addr, | 1348 addr, |
1211 reinterpret_cast<intptr_t>(instr)); | 1349 reinterpret_cast<intptr_t>(instr)); |
1212 MipsDebugger dbg(this); | 1350 DieOrDebug(); |
1213 dbg.Debug(); | |
1214 return 0; | 1351 return 0; |
1215 } | 1352 } |
1216 | 1353 |
1217 | 1354 |
1218 void Simulator::WriteW(int32_t addr, int value, Instruction* instr) { | 1355 uint32_t Simulator::ReadWU(int64_t addr, Instruction* instr) { |
| 1356 if (addr >=0 && addr < 0x400) { |
| 1357 // This has to be a NULL-dereference, drop into debugger. |
| 1358 PrintF("Memory read from bad address: 0x%08lx, pc=0x%08lx\n", |
| 1359 addr, reinterpret_cast<intptr_t>(instr)); |
| 1360 DieOrDebug(); |
| 1361 } |
| 1362 if ((addr & 0x3) == 0) { |
| 1363 uint32_t* ptr = reinterpret_cast<uint32_t*>(addr); |
| 1364 TraceMemRd(addr, static_cast<int64_t>(*ptr)); |
| 1365 return *ptr; |
| 1366 } |
| 1367 PrintF("Unaligned read at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
| 1368 addr, |
| 1369 reinterpret_cast<intptr_t>(instr)); |
| 1370 DieOrDebug(); |
| 1371 return 0; |
| 1372 } |
| 1373 |
| 1374 |
| 1375 void Simulator::WriteW(int64_t addr, int value, Instruction* instr) { |
1219 if (addr >= 0 && addr < 0x400) { | 1376 if (addr >= 0 && addr < 0x400) { |
1220 // This has to be a NULL-dereference, drop into debugger. | 1377 // This has to be a NULL-dereference, drop into debugger. |
1221 PrintF("Memory write to bad address: 0x%08x, pc=0x%08x\n", | 1378 PrintF("Memory write to bad address: 0x%08lx, pc=0x%08lx\n", |
1222 addr, reinterpret_cast<intptr_t>(instr)); | 1379 addr, reinterpret_cast<intptr_t>(instr)); |
1223 MipsDebugger dbg(this); | 1380 DieOrDebug(); |
1224 dbg.Debug(); | |
1225 } | 1381 } |
1226 if ((addr & kPointerAlignmentMask) == 0) { | 1382 if ((addr & 0x3) == 0) { |
1227 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); | 1383 TraceMemWr(addr, value, WORD); |
| 1384 int* ptr = reinterpret_cast<int*>(addr); |
1228 *ptr = value; | 1385 *ptr = value; |
1229 return; | 1386 return; |
1230 } | 1387 } |
1231 PrintF("Unaligned write at 0x%08x, pc=0x%08" V8PRIxPTR "\n", | 1388 PrintF("Unaligned write at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
1232 addr, | 1389 addr, |
1233 reinterpret_cast<intptr_t>(instr)); | 1390 reinterpret_cast<intptr_t>(instr)); |
1234 MipsDebugger dbg(this); | 1391 DieOrDebug(); |
1235 dbg.Debug(); | |
1236 } | 1392 } |
1237 | 1393 |
1238 | 1394 |
1239 double Simulator::ReadD(int32_t addr, Instruction* instr) { | 1395 int64_t Simulator::Read2W(int64_t addr, Instruction* instr) { |
| 1396 if (addr >=0 && addr < 0x400) { |
| 1397 // This has to be a NULL-dereference, drop into debugger. |
| 1398 PrintF("Memory read from bad address: 0x%08lx, pc=0x%08lx\n", |
| 1399 addr, reinterpret_cast<intptr_t>(instr)); |
| 1400 DieOrDebug(); |
| 1401 } |
| 1402 if ((addr & kPointerAlignmentMask) == 0) { |
| 1403 int64_t* ptr = reinterpret_cast<int64_t*>(addr); |
| 1404 TraceMemRd(addr, *ptr); |
| 1405 return *ptr; |
| 1406 } |
| 1407 PrintF("Unaligned read at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
| 1408 addr, |
| 1409 reinterpret_cast<intptr_t>(instr)); |
| 1410 DieOrDebug(); |
| 1411 return 0; |
| 1412 } |
| 1413 |
| 1414 |
| 1415 void Simulator::Write2W(int64_t addr, int64_t value, Instruction* instr) { |
| 1416 if (addr >= 0 && addr < 0x400) { |
| 1417 // This has to be a NULL-dereference, drop into debugger. |
| 1418 PrintF("Memory write to bad address: 0x%08lx, pc=0x%08lx\n", |
| 1419 addr, reinterpret_cast<intptr_t>(instr)); |
| 1420 DieOrDebug(); |
| 1421 } |
| 1422 if ((addr & kPointerAlignmentMask) == 0) { |
| 1423 TraceMemWr(addr, value, DWORD); |
| 1424 int64_t* ptr = reinterpret_cast<int64_t*>(addr); |
| 1425 *ptr = value; |
| 1426 return; |
| 1427 } |
| 1428 PrintF("Unaligned write at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
| 1429 addr, |
| 1430 reinterpret_cast<intptr_t>(instr)); |
| 1431 DieOrDebug(); |
| 1432 } |
| 1433 |
| 1434 |
| 1435 double Simulator::ReadD(int64_t addr, Instruction* instr) { |
1240 if ((addr & kDoubleAlignmentMask) == 0) { | 1436 if ((addr & kDoubleAlignmentMask) == 0) { |
1241 double* ptr = reinterpret_cast<double*>(addr); | 1437 double* ptr = reinterpret_cast<double*>(addr); |
1242 return *ptr; | 1438 return *ptr; |
1243 } | 1439 } |
1244 PrintF("Unaligned (double) read at 0x%08x, pc=0x%08" V8PRIxPTR "\n", | 1440 PrintF("Unaligned (double) read at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
1245 addr, | 1441 addr, |
1246 reinterpret_cast<intptr_t>(instr)); | 1442 reinterpret_cast<intptr_t>(instr)); |
1247 base::OS::Abort(); | 1443 base::OS::Abort(); |
1248 return 0; | 1444 return 0; |
1249 } | 1445 } |
1250 | 1446 |
1251 | 1447 |
1252 void Simulator::WriteD(int32_t addr, double value, Instruction* instr) { | 1448 void Simulator::WriteD(int64_t addr, double value, Instruction* instr) { |
1253 if ((addr & kDoubleAlignmentMask) == 0) { | 1449 if ((addr & kDoubleAlignmentMask) == 0) { |
1254 double* ptr = reinterpret_cast<double*>(addr); | 1450 double* ptr = reinterpret_cast<double*>(addr); |
1255 *ptr = value; | 1451 *ptr = value; |
1256 return; | 1452 return; |
1257 } | 1453 } |
1258 PrintF("Unaligned (double) write at 0x%08x, pc=0x%08" V8PRIxPTR "\n", | 1454 PrintF("Unaligned (double) write at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
1259 addr, | 1455 addr, |
1260 reinterpret_cast<intptr_t>(instr)); | 1456 reinterpret_cast<intptr_t>(instr)); |
1261 base::OS::Abort(); | 1457 DieOrDebug(); |
1262 } | 1458 } |
1263 | 1459 |
1264 | 1460 |
1265 uint16_t Simulator::ReadHU(int32_t addr, Instruction* instr) { | 1461 uint16_t Simulator::ReadHU(int64_t addr, Instruction* instr) { |
1266 if ((addr & 1) == 0) { | 1462 if ((addr & 1) == 0) { |
1267 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); | 1463 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); |
| 1464 TraceMemRd(addr, static_cast<int64_t>(*ptr)); |
1268 return *ptr; | 1465 return *ptr; |
1269 } | 1466 } |
1270 PrintF("Unaligned unsigned halfword read at 0x%08x, pc=0x%08" V8PRIxPTR "\n", | 1467 PrintF("Unaligned unsigned halfword read at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
1271 addr, | 1468 addr, |
1272 reinterpret_cast<intptr_t>(instr)); | 1469 reinterpret_cast<intptr_t>(instr)); |
1273 base::OS::Abort(); | 1470 DieOrDebug(); |
1274 return 0; | 1471 return 0; |
1275 } | 1472 } |
1276 | 1473 |
1277 | 1474 |
1278 int16_t Simulator::ReadH(int32_t addr, Instruction* instr) { | 1475 int16_t Simulator::ReadH(int64_t addr, Instruction* instr) { |
1279 if ((addr & 1) == 0) { | 1476 if ((addr & 1) == 0) { |
1280 int16_t* ptr = reinterpret_cast<int16_t*>(addr); | 1477 int16_t* ptr = reinterpret_cast<int16_t*>(addr); |
| 1478 TraceMemRd(addr, static_cast<int64_t>(*ptr)); |
1281 return *ptr; | 1479 return *ptr; |
1282 } | 1480 } |
1283 PrintF("Unaligned signed halfword read at 0x%08x, pc=0x%08" V8PRIxPTR "\n", | 1481 PrintF("Unaligned signed halfword read at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
1284 addr, | 1482 addr, |
1285 reinterpret_cast<intptr_t>(instr)); | 1483 reinterpret_cast<intptr_t>(instr)); |
1286 base::OS::Abort(); | 1484 DieOrDebug(); |
1287 return 0; | 1485 return 0; |
1288 } | 1486 } |
1289 | 1487 |
1290 | 1488 |
1291 void Simulator::WriteH(int32_t addr, uint16_t value, Instruction* instr) { | 1489 void Simulator::WriteH(int64_t addr, uint16_t value, Instruction* instr) { |
1292 if ((addr & 1) == 0) { | 1490 if ((addr & 1) == 0) { |
| 1491 TraceMemWr(addr, value, HALF); |
1293 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); | 1492 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); |
1294 *ptr = value; | 1493 *ptr = value; |
1295 return; | 1494 return; |
1296 } | 1495 } |
1297 PrintF("Unaligned unsigned halfword write at 0x%08x, pc=0x%08" V8PRIxPTR "\n", | 1496 PrintF( |
1298 addr, | 1497 "Unaligned unsigned halfword write at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
1299 reinterpret_cast<intptr_t>(instr)); | 1498 addr, |
1300 base::OS::Abort(); | 1499 reinterpret_cast<intptr_t>(instr)); |
| 1500 DieOrDebug(); |
1301 } | 1501 } |
1302 | 1502 |
1303 | 1503 |
1304 void Simulator::WriteH(int32_t addr, int16_t value, Instruction* instr) { | 1504 void Simulator::WriteH(int64_t addr, int16_t value, Instruction* instr) { |
1305 if ((addr & 1) == 0) { | 1505 if ((addr & 1) == 0) { |
| 1506 TraceMemWr(addr, value, HALF); |
1306 int16_t* ptr = reinterpret_cast<int16_t*>(addr); | 1507 int16_t* ptr = reinterpret_cast<int16_t*>(addr); |
1307 *ptr = value; | 1508 *ptr = value; |
1308 return; | 1509 return; |
1309 } | 1510 } |
1310 PrintF("Unaligned halfword write at 0x%08x, pc=0x%08" V8PRIxPTR "\n", | 1511 PrintF("Unaligned halfword write at 0x%08lx, pc=0x%08" V8PRIxPTR "\n", |
1311 addr, | 1512 addr, |
1312 reinterpret_cast<intptr_t>(instr)); | 1513 reinterpret_cast<intptr_t>(instr)); |
1313 base::OS::Abort(); | 1514 DieOrDebug(); |
1314 } | 1515 } |
1315 | 1516 |
1316 | 1517 |
1317 uint32_t Simulator::ReadBU(int32_t addr) { | 1518 uint32_t Simulator::ReadBU(int64_t addr) { |
1318 uint8_t* ptr = reinterpret_cast<uint8_t*>(addr); | 1519 uint8_t* ptr = reinterpret_cast<uint8_t*>(addr); |
| 1520 TraceMemRd(addr, static_cast<int64_t>(*ptr)); |
1319 return *ptr & 0xff; | 1521 return *ptr & 0xff; |
1320 } | 1522 } |
1321 | 1523 |
1322 | 1524 |
1323 int32_t Simulator::ReadB(int32_t addr) { | 1525 int32_t Simulator::ReadB(int64_t addr) { |
1324 int8_t* ptr = reinterpret_cast<int8_t*>(addr); | 1526 int8_t* ptr = reinterpret_cast<int8_t*>(addr); |
| 1527 TraceMemRd(addr, static_cast<int64_t>(*ptr)); |
1325 return *ptr; | 1528 return *ptr; |
1326 } | 1529 } |
1327 | 1530 |
1328 | 1531 |
1329 void Simulator::WriteB(int32_t addr, uint8_t value) { | 1532 void Simulator::WriteB(int64_t addr, uint8_t value) { |
| 1533 TraceMemWr(addr, value, BYTE); |
1330 uint8_t* ptr = reinterpret_cast<uint8_t*>(addr); | 1534 uint8_t* ptr = reinterpret_cast<uint8_t*>(addr); |
1331 *ptr = value; | 1535 *ptr = value; |
1332 } | 1536 } |
1333 | 1537 |
1334 | 1538 |
1335 void Simulator::WriteB(int32_t addr, int8_t value) { | 1539 void Simulator::WriteB(int64_t addr, int8_t value) { |
| 1540 TraceMemWr(addr, value, BYTE); |
1336 int8_t* ptr = reinterpret_cast<int8_t*>(addr); | 1541 int8_t* ptr = reinterpret_cast<int8_t*>(addr); |
1337 *ptr = value; | 1542 *ptr = value; |
1338 } | 1543 } |
1339 | 1544 |
1340 | 1545 |
1341 // Returns the limit of the stack area to enable checking for stack overflows. | 1546 // Returns the limit of the stack area to enable checking for stack overflows. |
1342 uintptr_t Simulator::StackLimit() const { | 1547 uintptr_t Simulator::StackLimit() const { |
1343 // Leave a safety margin of 1024 bytes to prevent overrunning the stack when | 1548 // Leave a safety margin of 1024 bytes to prevent overrunning the stack when |
1344 // pushing values. | 1549 // pushing values. |
1345 return reinterpret_cast<uintptr_t>(stack_) + 1024; | 1550 return reinterpret_cast<uintptr_t>(stack_) + 1024; |
1346 } | 1551 } |
1347 | 1552 |
1348 | 1553 |
1349 // Unsupported instructions use Format to print an error and stop execution. | 1554 // Unsupported instructions use Format to print an error and stop execution. |
1350 void Simulator::Format(Instruction* instr, const char* format) { | 1555 void Simulator::Format(Instruction* instr, const char* format) { |
1351 PrintF("Simulator found unsupported instruction:\n 0x%08x: %s\n", | 1556 PrintF("Simulator found unsupported instruction:\n 0x%08lx: %s\n", |
1352 reinterpret_cast<intptr_t>(instr), format); | 1557 reinterpret_cast<intptr_t>(instr), format); |
1353 UNIMPLEMENTED_MIPS(); | 1558 UNIMPLEMENTED_MIPS(); |
1354 } | 1559 } |
1355 | 1560 |
1356 | 1561 |
1357 // Calls into the V8 runtime are based on this very simple interface. | 1562 // Calls into the V8 runtime are based on this very simple interface. |
1358 // Note: To be able to return two values from some calls the code in runtime.cc | 1563 // Note: To be able to return two values from some calls the code in runtime.cc |
1359 // uses the ObjectPair which is essentially two 32-bit values stuffed into a | 1564 // uses the ObjectPair which is essentially two 32-bit values stuffed into a |
1360 // 64-bit value. With the code below we assume that all runtime calls return | 1565 // 64-bit value. With the code below we assume that all runtime calls return |
1361 // 64 bits of result. If they don't, the v1 result register contains a bogus | 1566 // 64 bits of result. If they don't, the v1 result register contains a bogus |
1362 // value, which is fine because it is caller-saved. | 1567 // value, which is fine because it is caller-saved. |
1363 typedef int64_t (*SimulatorRuntimeCall)(int32_t arg0, | 1568 |
1364 int32_t arg1, | 1569 struct ObjectPair { |
1365 int32_t arg2, | 1570 Object* x; |
1366 int32_t arg3, | 1571 Object* y; |
1367 int32_t arg4, | 1572 }; |
1368 int32_t arg5); | 1573 |
| 1574 typedef ObjectPair (*SimulatorRuntimeCall)(int64_t arg0, |
| 1575 int64_t arg1, |
| 1576 int64_t arg2, |
| 1577 int64_t arg3, |
| 1578 int64_t arg4, |
| 1579 int64_t arg5); |
| 1580 |
1369 | 1581 |
1370 // These prototypes handle the four types of FP calls. | 1582 // These prototypes handle the four types of FP calls. |
1371 typedef int64_t (*SimulatorRuntimeCompareCall)(double darg0, double darg1); | 1583 typedef int64_t (*SimulatorRuntimeCompareCall)(double darg0, double darg1); |
1372 typedef double (*SimulatorRuntimeFPFPCall)(double darg0, double darg1); | 1584 typedef double (*SimulatorRuntimeFPFPCall)(double darg0, double darg1); |
1373 typedef double (*SimulatorRuntimeFPCall)(double darg0); | 1585 typedef double (*SimulatorRuntimeFPCall)(double darg0); |
1374 typedef double (*SimulatorRuntimeFPIntCall)(double darg0, int32_t arg0); | 1586 typedef double (*SimulatorRuntimeFPIntCall)(double darg0, int32_t arg0); |
1375 | 1587 |
1376 // This signature supports direct call in to API function native callback | 1588 // This signature supports direct call in to API function native callback |
1377 // (refer to InvocationCallback in v8.h). | 1589 // (refer to InvocationCallback in v8.h). |
1378 typedef void (*SimulatorRuntimeDirectApiCall)(int32_t arg0); | 1590 typedef void (*SimulatorRuntimeDirectApiCall)(int64_t arg0); |
1379 typedef void (*SimulatorRuntimeProfilingApiCall)(int32_t arg0, void* arg1); | 1591 typedef void (*SimulatorRuntimeProfilingApiCall)(int64_t arg0, void* arg1); |
1380 | 1592 |
1381 // This signature supports direct call to accessor getter callback. | 1593 // This signature supports direct call to accessor getter callback. |
1382 typedef void (*SimulatorRuntimeDirectGetterCall)(int32_t arg0, int32_t arg1); | 1594 typedef void (*SimulatorRuntimeDirectGetterCall)(int64_t arg0, int64_t arg1); |
1383 typedef void (*SimulatorRuntimeProfilingGetterCall)( | 1595 typedef void (*SimulatorRuntimeProfilingGetterCall)( |
1384 int32_t arg0, int32_t arg1, void* arg2); | 1596 int64_t arg0, int64_t arg1, void* arg2); |
1385 | 1597 |
1386 // Software interrupt instructions are used by the simulator to call into the | 1598 // Software interrupt instructions are used by the simulator to call into the |
1387 // C-based V8 runtime. They are also used for debugging with simulator. | 1599 // C-based V8 runtime. They are also used for debugging with simulator. |
1388 void Simulator::SoftwareInterrupt(Instruction* instr) { | 1600 void Simulator::SoftwareInterrupt(Instruction* instr) { |
1389 // There are several instructions that could get us here, | 1601 // There are several instructions that could get us here, |
1390 // the break_ instruction, or several variants of traps. All | 1602 // the break_ instruction, or several variants of traps. All |
1391 // Are "SPECIAL" class opcode, and are distinuished by function. | 1603 // Are "SPECIAL" class opcode, and are distinuished by function. |
1392 int32_t func = instr->FunctionFieldRaw(); | 1604 int32_t func = instr->FunctionFieldRaw(); |
1393 uint32_t code = (func == BREAK) ? instr->Bits(25, 6) : -1; | 1605 uint32_t code = (func == BREAK) ? instr->Bits(25, 6) : -1; |
1394 | |
1395 // We first check if we met a call_rt_redirected. | 1606 // We first check if we met a call_rt_redirected. |
1396 if (instr->InstructionBits() == rtCallRedirInstr) { | 1607 if (instr->InstructionBits() == rtCallRedirInstr) { |
1397 Redirection* redirection = Redirection::FromSwiInstruction(instr); | 1608 Redirection* redirection = Redirection::FromSwiInstruction(instr); |
1398 int32_t arg0 = get_register(a0); | 1609 int64_t arg0 = get_register(a0); |
1399 int32_t arg1 = get_register(a1); | 1610 int64_t arg1 = get_register(a1); |
1400 int32_t arg2 = get_register(a2); | 1611 int64_t arg2 = get_register(a2); |
1401 int32_t arg3 = get_register(a3); | 1612 int64_t arg3 = get_register(a3); |
| 1613 int64_t arg4, arg5; |
1402 | 1614 |
1403 int32_t* stack_pointer = reinterpret_cast<int32_t*>(get_register(sp)); | 1615 if (kMipsAbi == kN64) { |
1404 // Args 4 and 5 are on the stack after the reserved space for args 0..3. | 1616 arg4 = get_register(a4); // Abi n64 register a4. |
1405 int32_t arg4 = stack_pointer[4]; | 1617 arg5 = get_register(a5); // Abi n64 register a5. |
1406 int32_t arg5 = stack_pointer[5]; | 1618 } else { // Abi O32. |
1407 | 1619 int64_t* stack_pointer = reinterpret_cast<int64_t*>(get_register(sp)); |
| 1620 // Args 4 and 5 are on the stack after the reserved space for args 0..3. |
| 1621 arg4 = stack_pointer[4]; |
| 1622 arg5 = stack_pointer[5]; |
| 1623 } |
1408 bool fp_call = | 1624 bool fp_call = |
1409 (redirection->type() == ExternalReference::BUILTIN_FP_FP_CALL) || | 1625 (redirection->type() == ExternalReference::BUILTIN_FP_FP_CALL) || |
1410 (redirection->type() == ExternalReference::BUILTIN_COMPARE_CALL) || | 1626 (redirection->type() == ExternalReference::BUILTIN_COMPARE_CALL) || |
1411 (redirection->type() == ExternalReference::BUILTIN_FP_CALL) || | 1627 (redirection->type() == ExternalReference::BUILTIN_FP_CALL) || |
1412 (redirection->type() == ExternalReference::BUILTIN_FP_INT_CALL); | 1628 (redirection->type() == ExternalReference::BUILTIN_FP_INT_CALL); |
1413 | 1629 |
1414 if (!IsMipsSoftFloatABI) { | 1630 if (!IsMipsSoftFloatABI) { |
1415 // With the hard floating point calling convention, double | 1631 // With the hard floating point calling convention, double |
1416 // arguments are passed in FPU registers. Fetch the arguments | 1632 // arguments are passed in FPU registers. Fetch the arguments |
1417 // from there and call the builtin using soft floating point | 1633 // from there and call the builtin using soft floating point |
(...skipping 15 matching lines...) Expand all Loading... |
1433 arg1 = get_fpu_register(f13); | 1649 arg1 = get_fpu_register(f13); |
1434 arg2 = get_register(a2); | 1650 arg2 = get_register(a2); |
1435 break; | 1651 break; |
1436 default: | 1652 default: |
1437 break; | 1653 break; |
1438 } | 1654 } |
1439 } | 1655 } |
1440 | 1656 |
1441 // This is dodgy but it works because the C entry stubs are never moved. | 1657 // This is dodgy but it works because the C entry stubs are never moved. |
1442 // See comment in codegen-arm.cc and bug 1242173. | 1658 // See comment in codegen-arm.cc and bug 1242173. |
1443 int32_t saved_ra = get_register(ra); | 1659 int64_t saved_ra = get_register(ra); |
1444 | 1660 |
1445 intptr_t external = | 1661 intptr_t external = |
1446 reinterpret_cast<intptr_t>(redirection->external_function()); | 1662 reinterpret_cast<intptr_t>(redirection->external_function()); |
1447 | 1663 |
1448 // Based on CpuFeatures::IsSupported(FPU), Mips will use either hardware | 1664 // Based on CpuFeatures::IsSupported(FPU), Mips will use either hardware |
1449 // FPU, or gcc soft-float routines. Hardware FPU is simulated in this | 1665 // FPU, or gcc soft-float routines. Hardware FPU is simulated in this |
1450 // simulator. Soft-float has additional abstraction of ExternalReference, | 1666 // simulator. Soft-float has additional abstraction of ExternalReference, |
1451 // to support serialization. | 1667 // to support serialization. |
1452 if (fp_call) { | 1668 if (fp_call) { |
1453 double dval0, dval1; // one or two double parameters | 1669 double dval0, dval1; // one or two double parameters |
(...skipping 21 matching lines...) Expand all Loading... |
1475 default: | 1691 default: |
1476 UNREACHABLE(); | 1692 UNREACHABLE(); |
1477 break; | 1693 break; |
1478 } | 1694 } |
1479 } | 1695 } |
1480 switch (redirection->type()) { | 1696 switch (redirection->type()) { |
1481 case ExternalReference::BUILTIN_COMPARE_CALL: { | 1697 case ExternalReference::BUILTIN_COMPARE_CALL: { |
1482 SimulatorRuntimeCompareCall target = | 1698 SimulatorRuntimeCompareCall target = |
1483 reinterpret_cast<SimulatorRuntimeCompareCall>(external); | 1699 reinterpret_cast<SimulatorRuntimeCompareCall>(external); |
1484 iresult = target(dval0, dval1); | 1700 iresult = target(dval0, dval1); |
1485 set_register(v0, static_cast<int32_t>(iresult)); | 1701 set_register(v0, static_cast<int64_t>(iresult)); |
1486 set_register(v1, static_cast<int32_t>(iresult >> 32)); | 1702 // set_register(v1, static_cast<int64_t>(iresult >> 32)); |
1487 break; | 1703 break; |
1488 } | 1704 } |
1489 case ExternalReference::BUILTIN_FP_FP_CALL: { | 1705 case ExternalReference::BUILTIN_FP_FP_CALL: { |
1490 SimulatorRuntimeFPFPCall target = | 1706 SimulatorRuntimeFPFPCall target = |
1491 reinterpret_cast<SimulatorRuntimeFPFPCall>(external); | 1707 reinterpret_cast<SimulatorRuntimeFPFPCall>(external); |
1492 dresult = target(dval0, dval1); | 1708 dresult = target(dval0, dval1); |
1493 SetFpResult(dresult); | 1709 SetFpResult(dresult); |
1494 break; | 1710 break; |
1495 } | 1711 } |
1496 case ExternalReference::BUILTIN_FP_CALL: { | 1712 case ExternalReference::BUILTIN_FP_CALL: { |
(...skipping 24 matching lines...) Expand all Loading... |
1521 case ExternalReference::BUILTIN_FP_INT_CALL: | 1737 case ExternalReference::BUILTIN_FP_INT_CALL: |
1522 PrintF("Returned %f\n", dresult); | 1738 PrintF("Returned %f\n", dresult); |
1523 break; | 1739 break; |
1524 default: | 1740 default: |
1525 UNREACHABLE(); | 1741 UNREACHABLE(); |
1526 break; | 1742 break; |
1527 } | 1743 } |
1528 } | 1744 } |
1529 } else if (redirection->type() == ExternalReference::DIRECT_API_CALL) { | 1745 } else if (redirection->type() == ExternalReference::DIRECT_API_CALL) { |
1530 if (::v8::internal::FLAG_trace_sim) { | 1746 if (::v8::internal::FLAG_trace_sim) { |
1531 PrintF("Call to host function at %p args %08x\n", | 1747 PrintF("Call to host function at %p args %08lx\n", |
1532 reinterpret_cast<void*>(external), arg0); | 1748 reinterpret_cast<void*>(external), arg0); |
1533 } | 1749 } |
1534 SimulatorRuntimeDirectApiCall target = | 1750 SimulatorRuntimeDirectApiCall target = |
1535 reinterpret_cast<SimulatorRuntimeDirectApiCall>(external); | 1751 reinterpret_cast<SimulatorRuntimeDirectApiCall>(external); |
1536 target(arg0); | 1752 target(arg0); |
1537 } else if ( | 1753 } else if ( |
1538 redirection->type() == ExternalReference::PROFILING_API_CALL) { | 1754 redirection->type() == ExternalReference::PROFILING_API_CALL) { |
1539 if (::v8::internal::FLAG_trace_sim) { | 1755 if (::v8::internal::FLAG_trace_sim) { |
1540 PrintF("Call to host function at %p args %08x %08x\n", | 1756 PrintF("Call to host function at %p args %08lx %08lx\n", |
1541 reinterpret_cast<void*>(external), arg0, arg1); | 1757 reinterpret_cast<void*>(external), arg0, arg1); |
1542 } | 1758 } |
1543 SimulatorRuntimeProfilingApiCall target = | 1759 SimulatorRuntimeProfilingApiCall target = |
1544 reinterpret_cast<SimulatorRuntimeProfilingApiCall>(external); | 1760 reinterpret_cast<SimulatorRuntimeProfilingApiCall>(external); |
1545 target(arg0, Redirection::ReverseRedirection(arg1)); | 1761 target(arg0, Redirection::ReverseRedirection(arg1)); |
1546 } else if ( | 1762 } else if ( |
1547 redirection->type() == ExternalReference::DIRECT_GETTER_CALL) { | 1763 redirection->type() == ExternalReference::DIRECT_GETTER_CALL) { |
1548 if (::v8::internal::FLAG_trace_sim) { | 1764 if (::v8::internal::FLAG_trace_sim) { |
1549 PrintF("Call to host function at %p args %08x %08x\n", | 1765 PrintF("Call to host function at %p args %08lx %08lx\n", |
1550 reinterpret_cast<void*>(external), arg0, arg1); | 1766 reinterpret_cast<void*>(external), arg0, arg1); |
1551 } | 1767 } |
1552 SimulatorRuntimeDirectGetterCall target = | 1768 SimulatorRuntimeDirectGetterCall target = |
1553 reinterpret_cast<SimulatorRuntimeDirectGetterCall>(external); | 1769 reinterpret_cast<SimulatorRuntimeDirectGetterCall>(external); |
1554 target(arg0, arg1); | 1770 target(arg0, arg1); |
1555 } else if ( | 1771 } else if ( |
1556 redirection->type() == ExternalReference::PROFILING_GETTER_CALL) { | 1772 redirection->type() == ExternalReference::PROFILING_GETTER_CALL) { |
1557 if (::v8::internal::FLAG_trace_sim) { | 1773 if (::v8::internal::FLAG_trace_sim) { |
1558 PrintF("Call to host function at %p args %08x %08x %08x\n", | 1774 PrintF("Call to host function at %p args %08lx %08lx %08lx\n", |
1559 reinterpret_cast<void*>(external), arg0, arg1, arg2); | 1775 reinterpret_cast<void*>(external), arg0, arg1, arg2); |
1560 } | 1776 } |
1561 SimulatorRuntimeProfilingGetterCall target = | 1777 SimulatorRuntimeProfilingGetterCall target = |
1562 reinterpret_cast<SimulatorRuntimeProfilingGetterCall>(external); | 1778 reinterpret_cast<SimulatorRuntimeProfilingGetterCall>(external); |
1563 target(arg0, arg1, Redirection::ReverseRedirection(arg2)); | 1779 target(arg0, arg1, Redirection::ReverseRedirection(arg2)); |
1564 } else { | 1780 } else { |
1565 SimulatorRuntimeCall target = | 1781 SimulatorRuntimeCall target = |
1566 reinterpret_cast<SimulatorRuntimeCall>(external); | 1782 reinterpret_cast<SimulatorRuntimeCall>(external); |
1567 if (::v8::internal::FLAG_trace_sim) { | 1783 if (::v8::internal::FLAG_trace_sim) { |
1568 PrintF( | 1784 PrintF( |
1569 "Call to host function at %p " | 1785 "Call to host function at %p " |
1570 "args %08x, %08x, %08x, %08x, %08x, %08x\n", | 1786 "args %08lx, %08lx, %08lx, %08lx, %08lx, %08lx\n", |
1571 FUNCTION_ADDR(target), | 1787 FUNCTION_ADDR(target), |
1572 arg0, | 1788 arg0, |
1573 arg1, | 1789 arg1, |
1574 arg2, | 1790 arg2, |
1575 arg3, | 1791 arg3, |
1576 arg4, | 1792 arg4, |
1577 arg5); | 1793 arg5); |
1578 } | 1794 } |
1579 int64_t result = target(arg0, arg1, arg2, arg3, arg4, arg5); | 1795 // int64_t result = target(arg0, arg1, arg2, arg3, arg4, arg5); |
1580 set_register(v0, static_cast<int32_t>(result)); | 1796 // set_register(v0, static_cast<int32_t>(result)); |
1581 set_register(v1, static_cast<int32_t>(result >> 32)); | 1797 // set_register(v1, static_cast<int32_t>(result >> 32)); |
| 1798 ObjectPair result = target(arg0, arg1, arg2, arg3, arg4, arg5); |
| 1799 set_register(v0, (int64_t)(result.x)); |
| 1800 set_register(v1, (int64_t)(result.y)); |
1582 } | 1801 } |
1583 if (::v8::internal::FLAG_trace_sim) { | 1802 if (::v8::internal::FLAG_trace_sim) { |
1584 PrintF("Returned %08x : %08x\n", get_register(v1), get_register(v0)); | 1803 PrintF("Returned %08lx : %08lx\n", get_register(v1), get_register(v0)); |
1585 } | 1804 } |
1586 set_register(ra, saved_ra); | 1805 set_register(ra, saved_ra); |
1587 set_pc(get_register(ra)); | 1806 set_pc(get_register(ra)); |
1588 | 1807 |
1589 } else if (func == BREAK && code <= kMaxStopCode) { | 1808 } else if (func == BREAK && code <= kMaxStopCode) { |
1590 if (IsWatchpoint(code)) { | 1809 if (IsWatchpoint(code)) { |
1591 PrintWatchpoint(code); | 1810 PrintWatchpoint(code); |
1592 } else { | 1811 } else { |
1593 IncreaseStopCounter(code); | 1812 IncreaseStopCounter(code); |
1594 HandleStop(code, instr); | 1813 HandleStop(code, instr); |
1595 } | 1814 } |
1596 } else { | 1815 } else { |
1597 // All remaining break_ codes, and all traps are handled here. | 1816 // All remaining break_ codes, and all traps are handled here. |
1598 MipsDebugger dbg(this); | 1817 MipsDebugger dbg(this); |
1599 dbg.Debug(); | 1818 dbg.Debug(); |
1600 } | 1819 } |
1601 } | 1820 } |
1602 | 1821 |
1603 | 1822 |
1604 // Stop helper functions. | 1823 // Stop helper functions. |
1605 bool Simulator::IsWatchpoint(uint32_t code) { | 1824 bool Simulator::IsWatchpoint(uint64_t code) { |
1606 return (code <= kMaxWatchpointCode); | 1825 return (code <= kMaxWatchpointCode); |
1607 } | 1826 } |
1608 | 1827 |
1609 | 1828 |
1610 void Simulator::PrintWatchpoint(uint32_t code) { | 1829 void Simulator::PrintWatchpoint(uint64_t code) { |
1611 MipsDebugger dbg(this); | 1830 MipsDebugger dbg(this); |
1612 ++break_count_; | 1831 ++break_count_; |
1613 PrintF("\n---- break %d marker: %3d (instr count: %8d) ----------" | 1832 PrintF("\n---- break %ld marker: %3d (instr count: %8ld) ----------" |
1614 "----------------------------------", | 1833 "----------------------------------", |
1615 code, break_count_, icount_); | 1834 code, break_count_, icount_); |
1616 dbg.PrintAllRegs(); // Print registers and continue running. | 1835 dbg.PrintAllRegs(); // Print registers and continue running. |
1617 } | 1836 } |
1618 | 1837 |
1619 | 1838 |
1620 void Simulator::HandleStop(uint32_t code, Instruction* instr) { | 1839 void Simulator::HandleStop(uint64_t code, Instruction* instr) { |
1621 // Stop if it is enabled, otherwise go on jumping over the stop | 1840 // Stop if it is enabled, otherwise go on jumping over the stop |
1622 // and the message address. | 1841 // and the message address. |
1623 if (IsEnabledStop(code)) { | 1842 if (IsEnabledStop(code)) { |
1624 MipsDebugger dbg(this); | 1843 MipsDebugger dbg(this); |
1625 dbg.Stop(instr); | 1844 dbg.Stop(instr); |
1626 } else { | 1845 } else { |
1627 set_pc(get_pc() + 2 * Instruction::kInstrSize); | 1846 set_pc(get_pc() + 2 * Instruction::kInstrSize); |
1628 } | 1847 } |
1629 } | 1848 } |
1630 | 1849 |
1631 | 1850 |
1632 bool Simulator::IsStopInstruction(Instruction* instr) { | 1851 bool Simulator::IsStopInstruction(Instruction* instr) { |
1633 int32_t func = instr->FunctionFieldRaw(); | 1852 int32_t func = instr->FunctionFieldRaw(); |
1634 uint32_t code = static_cast<uint32_t>(instr->Bits(25, 6)); | 1853 uint32_t code = static_cast<uint32_t>(instr->Bits(25, 6)); |
1635 return (func == BREAK) && code > kMaxWatchpointCode && code <= kMaxStopCode; | 1854 return (func == BREAK) && code > kMaxWatchpointCode && code <= kMaxStopCode; |
1636 } | 1855 } |
1637 | 1856 |
1638 | 1857 |
1639 bool Simulator::IsEnabledStop(uint32_t code) { | 1858 bool Simulator::IsEnabledStop(uint64_t code) { |
1640 ASSERT(code <= kMaxStopCode); | 1859 ASSERT(code <= kMaxStopCode); |
1641 ASSERT(code > kMaxWatchpointCode); | 1860 ASSERT(code > kMaxWatchpointCode); |
1642 return !(watched_stops_[code].count & kStopDisabledBit); | 1861 return !(watched_stops_[code].count & kStopDisabledBit); |
1643 } | 1862 } |
1644 | 1863 |
1645 | 1864 |
1646 void Simulator::EnableStop(uint32_t code) { | 1865 void Simulator::EnableStop(uint64_t code) { |
1647 if (!IsEnabledStop(code)) { | 1866 if (!IsEnabledStop(code)) { |
1648 watched_stops_[code].count &= ~kStopDisabledBit; | 1867 watched_stops_[code].count &= ~kStopDisabledBit; |
1649 } | 1868 } |
1650 } | 1869 } |
1651 | 1870 |
1652 | 1871 |
1653 void Simulator::DisableStop(uint32_t code) { | 1872 void Simulator::DisableStop(uint64_t code) { |
1654 if (IsEnabledStop(code)) { | 1873 if (IsEnabledStop(code)) { |
1655 watched_stops_[code].count |= kStopDisabledBit; | 1874 watched_stops_[code].count |= kStopDisabledBit; |
1656 } | 1875 } |
1657 } | 1876 } |
1658 | 1877 |
1659 | 1878 |
1660 void Simulator::IncreaseStopCounter(uint32_t code) { | 1879 void Simulator::IncreaseStopCounter(uint64_t code) { |
1661 ASSERT(code <= kMaxStopCode); | 1880 ASSERT(code <= kMaxStopCode); |
1662 if ((watched_stops_[code].count & ~(1 << 31)) == 0x7fffffff) { | 1881 if ((watched_stops_[code].count & ~(1 << 31)) == 0x7fffffff) { |
1663 PrintF("Stop counter for code %i has overflowed.\n" | 1882 PrintF("Stop counter for code %ld has overflowed.\n" |
1664 "Enabling this code and reseting the counter to 0.\n", code); | 1883 "Enabling this code and reseting the counter to 0.\n", code); |
1665 watched_stops_[code].count = 0; | 1884 watched_stops_[code].count = 0; |
1666 EnableStop(code); | 1885 EnableStop(code); |
1667 } else { | 1886 } else { |
1668 watched_stops_[code].count++; | 1887 watched_stops_[code].count++; |
1669 } | 1888 } |
1670 } | 1889 } |
1671 | 1890 |
1672 | 1891 |
1673 // Print a stop status. | 1892 // Print a stop status. |
1674 void Simulator::PrintStopInfo(uint32_t code) { | 1893 void Simulator::PrintStopInfo(uint64_t code) { |
1675 if (code <= kMaxWatchpointCode) { | 1894 if (code <= kMaxWatchpointCode) { |
1676 PrintF("That is a watchpoint, not a stop.\n"); | 1895 PrintF("That is a watchpoint, not a stop.\n"); |
1677 return; | 1896 return; |
1678 } else if (code > kMaxStopCode) { | 1897 } else if (code > kMaxStopCode) { |
1679 PrintF("Code too large, only %u stops can be used\n", kMaxStopCode + 1); | 1898 PrintF("Code too large, only %u stops can be used\n", kMaxStopCode + 1); |
1680 return; | 1899 return; |
1681 } | 1900 } |
1682 const char* state = IsEnabledStop(code) ? "Enabled" : "Disabled"; | 1901 const char* state = IsEnabledStop(code) ? "Enabled" : "Disabled"; |
1683 int32_t count = watched_stops_[code].count & ~kStopDisabledBit; | 1902 int32_t count = watched_stops_[code].count & ~kStopDisabledBit; |
1684 // Don't print the state of unused breakpoints. | 1903 // Don't print the state of unused breakpoints. |
1685 if (count != 0) { | 1904 if (count != 0) { |
1686 if (watched_stops_[code].desc) { | 1905 if (watched_stops_[code].desc) { |
1687 PrintF("stop %i - 0x%x: \t%s, \tcounter = %i, \t%s\n", | 1906 PrintF("stop %ld - 0x%lx: \t%s, \tcounter = %i, \t%s\n", |
1688 code, code, state, count, watched_stops_[code].desc); | 1907 code, code, state, count, watched_stops_[code].desc); |
1689 } else { | 1908 } else { |
1690 PrintF("stop %i - 0x%x: \t%s, \tcounter = %i\n", | 1909 PrintF("stop %ld - 0x%lx: \t%s, \tcounter = %i\n", |
1691 code, code, state, count); | 1910 code, code, state, count); |
1692 } | 1911 } |
1693 } | 1912 } |
1694 } | 1913 } |
1695 | 1914 |
1696 | 1915 |
1697 void Simulator::SignalExceptions() { | 1916 void Simulator::SignalExceptions() { |
1698 for (int i = 1; i < kNumExceptions; i++) { | 1917 for (int i = 1; i < kNumExceptions; i++) { |
1699 if (exceptions[i] != 0) { | 1918 if (exceptions[i] != 0) { |
1700 V8_Fatal(__FILE__, __LINE__, "Error: Exception %i raised.", i); | 1919 V8_Fatal(__FILE__, __LINE__, "Error: Exception %i raised.", i); |
1701 } | 1920 } |
1702 } | 1921 } |
1703 } | 1922 } |
1704 | 1923 |
1705 | 1924 |
1706 // Handle execution based on instruction types. | 1925 // Handle execution based on instruction types. |
1707 | 1926 |
1708 void Simulator::ConfigureTypeRegister(Instruction* instr, | 1927 void Simulator::ConfigureTypeRegister(Instruction* instr, |
1709 int32_t* alu_out, | 1928 int64_t* alu_out, |
1710 int64_t* i64hilo, | 1929 int64_t* i64hilo, |
1711 uint64_t* u64hilo, | 1930 uint64_t* u64hilo, |
1712 int32_t* next_pc, | 1931 int64_t* next_pc, |
1713 int32_t* return_addr_reg, | 1932 int64_t* return_addr_reg, |
1714 bool* do_interrupt) { | 1933 bool* do_interrupt, |
| 1934 int64_t* i128resultH, |
| 1935 int64_t* i128resultL) { |
1715 // Every local variable declared here needs to be const. | 1936 // Every local variable declared here needs to be const. |
1716 // This is to make sure that changed values are sent back to | 1937 // This is to make sure that changed values are sent back to |
1717 // DecodeTypeRegister correctly. | 1938 // DecodeTypeRegister correctly. |
1718 | 1939 |
1719 // Instruction fields. | 1940 // Instruction fields. |
1720 const Opcode op = instr->OpcodeFieldRaw(); | 1941 const Opcode op = instr->OpcodeFieldRaw(); |
1721 const int32_t rs_reg = instr->RsValue(); | 1942 const int64_t rs_reg = instr->RsValue(); |
1722 const int32_t rs = get_register(rs_reg); | 1943 const int64_t rs = get_register(rs_reg); |
1723 const uint32_t rs_u = static_cast<uint32_t>(rs); | 1944 const uint64_t rs_u = static_cast<uint64_t>(rs); |
1724 const int32_t rt_reg = instr->RtValue(); | 1945 const int64_t rt_reg = instr->RtValue(); |
1725 const int32_t rt = get_register(rt_reg); | 1946 const int64_t rt = get_register(rt_reg); |
1726 const uint32_t rt_u = static_cast<uint32_t>(rt); | 1947 const uint64_t rt_u = static_cast<uint64_t>(rt); |
1727 const int32_t rd_reg = instr->RdValue(); | 1948 const int64_t rd_reg = instr->RdValue(); |
1728 const uint32_t sa = instr->SaValue(); | 1949 const uint64_t sa = instr->SaValue(); |
1729 | 1950 |
1730 const int32_t fs_reg = instr->FsValue(); | 1951 const int32_t fs_reg = instr->FsValue(); |
1731 | 1952 |
1732 | 1953 |
1733 // ---------- Configuration. | 1954 // ---------- Configuration. |
1734 switch (op) { | 1955 switch (op) { |
1735 case COP1: // Coprocessor instructions. | 1956 case COP1: // Coprocessor instructions. |
1736 switch (instr->RsFieldRaw()) { | 1957 switch (instr->RsFieldRaw()) { |
1737 case BC1: // Handled in DecodeTypeImmed, should never come here. | 1958 case BC1: // Handled in DecodeTypeImmed, should never come here. |
1738 UNREACHABLE(); | 1959 UNREACHABLE(); |
1739 break; | 1960 break; |
1740 case CFC1: | 1961 case CFC1: |
1741 // At the moment only FCSR is supported. | 1962 // At the moment only FCSR is supported. |
1742 ASSERT(fs_reg == kFCSRRegister); | 1963 ASSERT(fs_reg == kFCSRRegister); |
1743 *alu_out = FCSR_; | 1964 *alu_out = FCSR_; |
1744 break; | 1965 break; |
1745 case MFC1: | 1966 case MFC1: |
| 1967 *alu_out = static_cast<int64_t>(get_fpu_register_word(fs_reg)); |
| 1968 break; |
| 1969 case DMFC1: |
1746 *alu_out = get_fpu_register(fs_reg); | 1970 *alu_out = get_fpu_register(fs_reg); |
1747 break; | 1971 break; |
1748 case MFHC1: | 1972 case MFHC1: |
1749 UNIMPLEMENTED_MIPS(); | 1973 *alu_out = get_fpu_register_hi_word(fs_reg); |
1750 break; | 1974 break; |
1751 case CTC1: | 1975 case CTC1: |
1752 case MTC1: | 1976 case MTC1: |
| 1977 case DMTC1: |
1753 case MTHC1: | 1978 case MTHC1: |
1754 // Do the store in the execution step. | 1979 // Do the store in the execution step. |
1755 break; | 1980 break; |
1756 case S: | 1981 case S: |
1757 case D: | 1982 case D: |
1758 case W: | 1983 case W: |
1759 case L: | 1984 case L: |
1760 case PS: | 1985 case PS: |
1761 // Do everything in the execution step. | 1986 // Do everything in the execution step. |
1762 break; | 1987 break; |
1763 default: | 1988 default: |
1764 UNIMPLEMENTED_MIPS(); | 1989 UNIMPLEMENTED_MIPS(); |
1765 } | 1990 } |
1766 break; | 1991 break; |
1767 case COP1X: | 1992 case COP1X: |
1768 break; | 1993 break; |
1769 case SPECIAL: | 1994 case SPECIAL: |
1770 switch (instr->FunctionFieldRaw()) { | 1995 switch (instr->FunctionFieldRaw()) { |
1771 case JR: | 1996 case JR: |
1772 case JALR: | 1997 case JALR: |
1773 *next_pc = get_register(instr->RsValue()); | 1998 *next_pc = get_register(instr->RsValue()); |
1774 *return_addr_reg = instr->RdValue(); | 1999 *return_addr_reg = instr->RdValue(); |
1775 break; | 2000 break; |
1776 case SLL: | 2001 case SLL: |
| 2002 *alu_out = (int32_t)rt << sa; |
| 2003 break; |
| 2004 case DSLL: |
1777 *alu_out = rt << sa; | 2005 *alu_out = rt << sa; |
1778 break; | 2006 break; |
| 2007 case DSLL32: |
| 2008 *alu_out = rt << sa << 32; |
| 2009 break; |
1779 case SRL: | 2010 case SRL: |
1780 if (rs_reg == 0) { | 2011 if (rs_reg == 0) { |
1781 // Regular logical right shift of a word by a fixed number of | 2012 // Regular logical right shift of a word by a fixed number of |
1782 // bits instruction. RS field is always equal to 0. | 2013 // bits instruction. RS field is always equal to 0. |
1783 *alu_out = rt_u >> sa; | 2014 *alu_out = (uint32_t)rt_u >> sa; |
1784 } else { | 2015 } else { |
1785 // Logical right-rotate of a word by a fixed number of bits. This | 2016 // Logical right-rotate of a word by a fixed number of bits. This |
1786 // is special case of SRL instruction, added in MIPS32 Release 2. | 2017 // is special case of SRL instruction, added in MIPS32 Release 2. |
1787 // RS field is equal to 00001. | 2018 // RS field is equal to 00001. |
1788 *alu_out = (rt_u >> sa) | (rt_u << (32 - sa)); | 2019 *alu_out = ((uint32_t)rt_u >> sa) | ((uint32_t)rt_u << (32 - sa)); |
1789 } | 2020 } |
1790 break; | 2021 break; |
| 2022 case DSRL: |
| 2023 *alu_out = rt_u >> sa; |
| 2024 break; |
| 2025 case DSRL32: |
| 2026 *alu_out = rt_u >> sa >> 32; |
| 2027 break; |
1791 case SRA: | 2028 case SRA: |
| 2029 *alu_out = (int32_t)rt >> sa; |
| 2030 break; |
| 2031 case DSRA: |
1792 *alu_out = rt >> sa; | 2032 *alu_out = rt >> sa; |
1793 break; | 2033 break; |
| 2034 case DSRA32: |
| 2035 *alu_out = rt >> sa >> 32; |
| 2036 break; |
1794 case SLLV: | 2037 case SLLV: |
| 2038 *alu_out = (int32_t)rt << rs; |
| 2039 break; |
| 2040 case DSLLV: |
1795 *alu_out = rt << rs; | 2041 *alu_out = rt << rs; |
1796 break; | 2042 break; |
1797 case SRLV: | 2043 case SRLV: |
1798 if (sa == 0) { | 2044 if (sa == 0) { |
1799 // Regular logical right-shift of a word by a variable number of | 2045 // Regular logical right-shift of a word by a variable number of |
1800 // bits instruction. SA field is always equal to 0. | 2046 // bits instruction. SA field is always equal to 0. |
| 2047 *alu_out = (uint32_t)rt_u >> rs; |
| 2048 } else { |
| 2049 // Logical right-rotate of a word by a variable number of bits. |
| 2050 // This is special case od SRLV instruction, added in MIPS32 |
| 2051 // Release 2. SA field is equal to 00001. |
| 2052 *alu_out = |
| 2053 ((uint32_t)rt_u >> rs_u) | ((uint32_t)rt_u << (32 - rs_u)); |
| 2054 } |
| 2055 break; |
| 2056 case DSRLV: |
| 2057 if (sa == 0) { |
| 2058 // Regular logical right-shift of a word by a variable number of |
| 2059 // bits instruction. SA field is always equal to 0. |
1801 *alu_out = rt_u >> rs; | 2060 *alu_out = rt_u >> rs; |
1802 } else { | 2061 } else { |
1803 // Logical right-rotate of a word by a variable number of bits. | 2062 // Logical right-rotate of a word by a variable number of bits. |
1804 // This is special case od SRLV instruction, added in MIPS32 | 2063 // This is special case od SRLV instruction, added in MIPS32 |
1805 // Release 2. SA field is equal to 00001. | 2064 // Release 2. SA field is equal to 00001. |
1806 *alu_out = (rt_u >> rs_u) | (rt_u << (32 - rs_u)); | 2065 *alu_out = (rt_u >> rs_u) | (rt_u << (32 - rs_u)); |
1807 } | 2066 } |
1808 break; | 2067 break; |
1809 case SRAV: | 2068 case SRAV: |
| 2069 *alu_out = (int32_t)rt >> rs; |
| 2070 break; |
| 2071 case DSRAV: |
1810 *alu_out = rt >> rs; | 2072 *alu_out = rt >> rs; |
1811 break; | 2073 break; |
1812 case MFHI: | 2074 case MFHI: |
1813 *alu_out = get_register(HI); | 2075 *alu_out = get_register(HI); |
1814 break; | 2076 break; |
1815 case MFLO: | 2077 case MFLO: |
1816 *alu_out = get_register(LO); | 2078 *alu_out = get_register(LO); |
1817 break; | 2079 break; |
1818 case MULT: | 2080 case MULT: |
1819 *i64hilo = static_cast<int64_t>(rs) * static_cast<int64_t>(rt); | 2081 // TODO(plind) - Unify MULT/DMULT with single set of 64-bit HI/Lo |
| 2082 // regs. |
| 2083 // TODO(plind) - make the 32-bit MULT ops conform to spec regarding |
| 2084 // checking of 32-bit input values, and un-define operations of HW. |
| 2085 *i64hilo = static_cast<int64_t>((int32_t)rs) * |
| 2086 static_cast<int64_t>((int32_t)rt); |
1820 break; | 2087 break; |
1821 case MULTU: | 2088 case MULTU: |
1822 *u64hilo = static_cast<uint64_t>(rs_u) * static_cast<uint64_t>(rt_u); | 2089 *u64hilo = static_cast<uint64_t>(rs_u) * static_cast<uint64_t>(rt_u); |
1823 break; | 2090 break; |
| 2091 case DMULT: |
| 2092 *i128resultH = MultiplyHighSigned(rs, rt); |
| 2093 *i128resultL = rs * rt; |
| 2094 break; |
| 2095 case DMULTU: |
| 2096 UNIMPLEMENTED_MIPS(); |
| 2097 break; |
1824 case ADD: | 2098 case ADD: |
| 2099 case DADD: |
1825 if (HaveSameSign(rs, rt)) { | 2100 if (HaveSameSign(rs, rt)) { |
1826 if (rs > 0) { | 2101 if (rs > 0) { |
1827 exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - rt); | 2102 exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - rt); |
1828 } else if (rs < 0) { | 2103 } else if (rs < 0) { |
1829 exceptions[kIntegerUnderflow] = rs < (Registers::kMinValue - rt); | 2104 exceptions[kIntegerUnderflow] = rs < (Registers::kMinValue - rt); |
1830 } | 2105 } |
1831 } | 2106 } |
1832 *alu_out = rs + rt; | 2107 *alu_out = rs + rt; |
1833 break; | 2108 break; |
1834 case ADDU: | 2109 case ADDU: { |
| 2110 int32_t alu32_out = rs + rt; |
| 2111 // Sign-extend result of 32bit operation into 64bit register. |
| 2112 *alu_out = static_cast<int64_t>(alu32_out); |
| 2113 } |
| 2114 break; |
| 2115 case DADDU: |
1835 *alu_out = rs + rt; | 2116 *alu_out = rs + rt; |
1836 break; | 2117 break; |
1837 case SUB: | 2118 case SUB: |
| 2119 case DSUB: |
1838 if (!HaveSameSign(rs, rt)) { | 2120 if (!HaveSameSign(rs, rt)) { |
1839 if (rs > 0) { | 2121 if (rs > 0) { |
1840 exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue + rt); | 2122 exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue + rt); |
1841 } else if (rs < 0) { | 2123 } else if (rs < 0) { |
1842 exceptions[kIntegerUnderflow] = rs < (Registers::kMinValue + rt); | 2124 exceptions[kIntegerUnderflow] = rs < (Registers::kMinValue + rt); |
1843 } | 2125 } |
1844 } | 2126 } |
1845 *alu_out = rs - rt; | 2127 *alu_out = rs - rt; |
1846 break; | 2128 break; |
1847 case SUBU: | 2129 case SUBU: { |
| 2130 int32_t alu32_out = rs - rt; |
| 2131 // Sign-extend result of 32bit operation into 64bit register. |
| 2132 *alu_out = static_cast<int64_t>(alu32_out); |
| 2133 } |
| 2134 break; |
| 2135 case DSUBU: |
1848 *alu_out = rs - rt; | 2136 *alu_out = rs - rt; |
1849 break; | 2137 break; |
1850 case AND: | 2138 case AND: |
1851 *alu_out = rs & rt; | 2139 *alu_out = rs & rt; |
1852 break; | 2140 break; |
1853 case OR: | 2141 case OR: |
1854 *alu_out = rs | rt; | 2142 *alu_out = rs | rt; |
1855 break; | 2143 break; |
1856 case XOR: | 2144 case XOR: |
1857 *alu_out = rs ^ rt; | 2145 *alu_out = rs ^ rt; |
1858 break; | 2146 break; |
1859 case NOR: | 2147 case NOR: |
1860 *alu_out = ~(rs | rt); | 2148 *alu_out = ~(rs | rt); |
1861 break; | 2149 break; |
1862 case SLT: | 2150 case SLT: |
1863 *alu_out = rs < rt ? 1 : 0; | 2151 *alu_out = rs < rt ? 1 : 0; |
1864 break; | 2152 break; |
1865 case SLTU: | 2153 case SLTU: |
1866 *alu_out = rs_u < rt_u ? 1 : 0; | 2154 *alu_out = rs_u < rt_u ? 1 : 0; |
1867 break; | 2155 break; |
1868 // Break and trap instructions. | 2156 // Break and trap instructions. |
1869 case BREAK: | 2157 case BREAK: |
| 2158 |
1870 *do_interrupt = true; | 2159 *do_interrupt = true; |
1871 break; | 2160 break; |
1872 case TGE: | 2161 case TGE: |
1873 *do_interrupt = rs >= rt; | 2162 *do_interrupt = rs >= rt; |
1874 break; | 2163 break; |
1875 case TGEU: | 2164 case TGEU: |
1876 *do_interrupt = rs_u >= rt_u; | 2165 *do_interrupt = rs_u >= rt_u; |
1877 break; | 2166 break; |
1878 case TLT: | 2167 case TLT: |
1879 *do_interrupt = rs < rt; | 2168 *do_interrupt = rs < rt; |
1880 break; | 2169 break; |
1881 case TLTU: | 2170 case TLTU: |
1882 *do_interrupt = rs_u < rt_u; | 2171 *do_interrupt = rs_u < rt_u; |
1883 break; | 2172 break; |
1884 case TEQ: | 2173 case TEQ: |
1885 *do_interrupt = rs == rt; | 2174 *do_interrupt = rs == rt; |
1886 break; | 2175 break; |
1887 case TNE: | 2176 case TNE: |
1888 *do_interrupt = rs != rt; | 2177 *do_interrupt = rs != rt; |
1889 break; | 2178 break; |
1890 case MOVN: | 2179 case MOVN: |
1891 case MOVZ: | 2180 case MOVZ: |
1892 case MOVCI: | 2181 case MOVCI: |
1893 // No action taken on decode. | 2182 // No action taken on decode. |
1894 break; | 2183 break; |
1895 case DIV: | 2184 case DIV: |
1896 case DIVU: | 2185 case DIVU: |
| 2186 case DDIV: |
| 2187 case DDIVU: |
1897 // div and divu never raise exceptions. | 2188 // div and divu never raise exceptions. |
1898 break; | 2189 break; |
1899 default: | 2190 default: |
1900 UNREACHABLE(); | 2191 UNREACHABLE(); |
1901 } | 2192 } |
1902 break; | 2193 break; |
1903 case SPECIAL2: | 2194 case SPECIAL2: |
1904 switch (instr->FunctionFieldRaw()) { | 2195 switch (instr->FunctionFieldRaw()) { |
1905 case MUL: | 2196 case MUL: |
1906 *alu_out = rs_u * rt_u; // Only the lower 32 bits are kept. | 2197 // Only the lower 32 bits are kept. |
| 2198 *alu_out = (int32_t)rs_u * (int32_t)rt_u; |
1907 break; | 2199 break; |
1908 case CLZ: | 2200 case CLZ: |
1909 // MIPS32 spec: If no bits were set in GPR rs, the result written to | 2201 // MIPS32 spec: If no bits were set in GPR rs, the result written to |
1910 // GPR rd is 32. | 2202 // GPR rd is 32. |
1911 // GCC __builtin_clz: If input is 0, the result is undefined. | 2203 // GCC __builtin_clz: If input is 0, the result is undefined. |
1912 *alu_out = | 2204 *alu_out = |
1913 rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u); | 2205 rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u); |
1914 break; | 2206 break; |
1915 default: | 2207 default: |
1916 UNREACHABLE(); | 2208 UNREACHABLE(); |
(...skipping 27 matching lines...) Expand all Loading... |
1944 break; | 2236 break; |
1945 default: | 2237 default: |
1946 UNREACHABLE(); | 2238 UNREACHABLE(); |
1947 } | 2239 } |
1948 } | 2240 } |
1949 | 2241 |
1950 | 2242 |
1951 void Simulator::DecodeTypeRegister(Instruction* instr) { | 2243 void Simulator::DecodeTypeRegister(Instruction* instr) { |
1952 // Instruction fields. | 2244 // Instruction fields. |
1953 const Opcode op = instr->OpcodeFieldRaw(); | 2245 const Opcode op = instr->OpcodeFieldRaw(); |
1954 const int32_t rs_reg = instr->RsValue(); | 2246 const int64_t rs_reg = instr->RsValue(); |
1955 const int32_t rs = get_register(rs_reg); | 2247 const int64_t rs = get_register(rs_reg); |
1956 const uint32_t rs_u = static_cast<uint32_t>(rs); | 2248 const uint64_t rs_u = static_cast<uint32_t>(rs); |
1957 const int32_t rt_reg = instr->RtValue(); | 2249 const int64_t rt_reg = instr->RtValue(); |
1958 const int32_t rt = get_register(rt_reg); | 2250 const int64_t rt = get_register(rt_reg); |
1959 const uint32_t rt_u = static_cast<uint32_t>(rt); | 2251 const uint64_t rt_u = static_cast<uint32_t>(rt); |
1960 const int32_t rd_reg = instr->RdValue(); | 2252 const int64_t rd_reg = instr->RdValue(); |
1961 | 2253 |
1962 const int32_t fr_reg = instr->FrValue(); | 2254 const int32_t fr_reg = instr->FrValue(); |
1963 const int32_t fs_reg = instr->FsValue(); | 2255 const int32_t fs_reg = instr->FsValue(); |
1964 const int32_t ft_reg = instr->FtValue(); | 2256 const int32_t ft_reg = instr->FtValue(); |
1965 const int32_t fd_reg = instr->FdValue(); | 2257 const int64_t fd_reg = instr->FdValue(); |
1966 int64_t i64hilo = 0; | 2258 int64_t i64hilo = 0; |
1967 uint64_t u64hilo = 0; | 2259 uint64_t u64hilo = 0; |
1968 | 2260 |
1969 // ALU output. | 2261 // ALU output. |
1970 // It should not be used as is. Instructions using it should always | 2262 // It should not be used as is. Instructions using it should always |
1971 // initialize it first. | 2263 // initialize it first. |
1972 int32_t alu_out = 0x12345678; | 2264 int64_t alu_out = 0x12345678; |
1973 | 2265 |
1974 // For break and trap instructions. | 2266 // For break and trap instructions. |
1975 bool do_interrupt = false; | 2267 bool do_interrupt = false; |
1976 | 2268 |
1977 // For jr and jalr. | 2269 // For jr and jalr. |
1978 // Get current pc. | 2270 // Get current pc. |
1979 int32_t current_pc = get_pc(); | 2271 int64_t current_pc = get_pc(); |
1980 // Next pc | 2272 // Next pc |
1981 int32_t next_pc = 0; | 2273 int64_t next_pc = 0; |
1982 int32_t return_addr_reg = 31; | 2274 int64_t return_addr_reg = 31; |
| 2275 |
| 2276 int64_t i128resultH; |
| 2277 int64_t i128resultL; |
1983 | 2278 |
1984 // Set up the variables if needed before executing the instruction. | 2279 // Set up the variables if needed before executing the instruction. |
1985 ConfigureTypeRegister(instr, | 2280 ConfigureTypeRegister(instr, |
1986 &alu_out, | 2281 &alu_out, |
1987 &i64hilo, | 2282 &i64hilo, |
1988 &u64hilo, | 2283 &u64hilo, |
1989 &next_pc, | 2284 &next_pc, |
1990 &return_addr_reg, | 2285 &return_addr_reg, |
1991 &do_interrupt); | 2286 &do_interrupt, |
| 2287 &i128resultH, |
| 2288 &i128resultL); |
1992 | 2289 |
1993 // ---------- Raise exceptions triggered. | 2290 // ---------- Raise exceptions triggered. |
1994 SignalExceptions(); | 2291 SignalExceptions(); |
1995 | 2292 |
1996 // ---------- Execution. | 2293 // ---------- Execution. |
1997 switch (op) { | 2294 switch (op) { |
1998 case COP1: | 2295 case COP1: |
1999 switch (instr->RsFieldRaw()) { | 2296 switch (instr->RsFieldRaw()) { |
2000 case BC1: // Branch on coprocessor condition. | 2297 case BC1: // Branch on coprocessor condition. |
2001 UNREACHABLE(); | 2298 UNREACHABLE(); |
2002 break; | 2299 break; |
2003 case CFC1: | 2300 case CFC1: |
2004 set_register(rt_reg, alu_out); | 2301 set_register(rt_reg, alu_out); |
| 2302 break; |
2005 case MFC1: | 2303 case MFC1: |
| 2304 case DMFC1: |
| 2305 case MFHC1: |
2006 set_register(rt_reg, alu_out); | 2306 set_register(rt_reg, alu_out); |
2007 break; | 2307 break; |
2008 case MFHC1: | |
2009 UNIMPLEMENTED_MIPS(); | |
2010 break; | |
2011 case CTC1: | 2308 case CTC1: |
2012 // At the moment only FCSR is supported. | 2309 // At the moment only FCSR is supported. |
2013 ASSERT(fs_reg == kFCSRRegister); | 2310 ASSERT(fs_reg == kFCSRRegister); |
2014 FCSR_ = registers_[rt_reg]; | 2311 FCSR_ = registers_[rt_reg]; |
2015 break; | 2312 break; |
2016 case MTC1: | 2313 case MTC1: |
2017 FPUregisters_[fs_reg] = registers_[rt_reg]; | 2314 // Hardware writes upper 32-bits to zero on mtc1. |
| 2315 set_fpu_register_hi_word(fs_reg, 0); |
| 2316 set_fpu_register_word(fs_reg, registers_[rt_reg]); |
| 2317 break; |
| 2318 case DMTC1: |
| 2319 set_fpu_register(fs_reg, registers_[rt_reg]); |
2018 break; | 2320 break; |
2019 case MTHC1: | 2321 case MTHC1: |
2020 UNIMPLEMENTED_MIPS(); | 2322 set_fpu_register_hi_word(fs_reg, registers_[rt_reg]); |
2021 break; | 2323 break; |
2022 case S: | 2324 case S: |
2023 float f; | 2325 float f; |
2024 switch (instr->FunctionFieldRaw()) { | 2326 switch (instr->FunctionFieldRaw()) { |
2025 case CVT_D_S: | 2327 case CVT_D_S: |
2026 f = get_fpu_register_float(fs_reg); | 2328 f = get_fpu_register_float(fs_reg); |
2027 set_fpu_register_double(fd_reg, static_cast<double>(f)); | 2329 set_fpu_register_double(fd_reg, static_cast<double>(f)); |
2028 break; | 2330 break; |
2029 case CVT_W_S: | 2331 case CVT_W_S: |
2030 case CVT_L_S: | 2332 case CVT_L_S: |
(...skipping 66 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2097 set_fcsr_bit(fcsr_cc, (fs <= ft)); | 2399 set_fcsr_bit(fcsr_cc, (fs <= ft)); |
2098 break; | 2400 break; |
2099 case C_ULE_D: | 2401 case C_ULE_D: |
2100 set_fcsr_bit(fcsr_cc, | 2402 set_fcsr_bit(fcsr_cc, |
2101 (fs <= ft) || (std::isnan(fs) || std::isnan(ft))); | 2403 (fs <= ft) || (std::isnan(fs) || std::isnan(ft))); |
2102 break; | 2404 break; |
2103 case CVT_W_D: // Convert double to word. | 2405 case CVT_W_D: // Convert double to word. |
2104 // Rounding modes are not yet supported. | 2406 // Rounding modes are not yet supported. |
2105 ASSERT((FCSR_ & 3) == 0); | 2407 ASSERT((FCSR_ & 3) == 0); |
2106 // In rounding mode 0 it should behave like ROUND. | 2408 // In rounding mode 0 it should behave like ROUND. |
| 2409 // No break. |
2107 case ROUND_W_D: // Round double to word (round half to even). | 2410 case ROUND_W_D: // Round double to word (round half to even). |
2108 { | 2411 { |
2109 double rounded = std::floor(fs + 0.5); | 2412 double rounded = std::floor(fs + 0.5); |
2110 int32_t result = static_cast<int32_t>(rounded); | 2413 int32_t result = static_cast<int32_t>(rounded); |
2111 if ((result & 1) != 0 && result - fs == 0.5) { | 2414 if ((result & 1) != 0 && result - fs == 0.5) { |
2112 // If the number is halfway between two integers, | 2415 // If the number is halfway between two integers, |
2113 // round to the even one. | 2416 // round to the even one. |
2114 result--; | 2417 result--; |
2115 } | 2418 } |
2116 set_fpu_register(fd_reg, result); | 2419 set_fpu_register_word(fd_reg, result); |
2117 if (set_fcsr_round_error(fs, rounded)) { | 2420 if (set_fcsr_round_error(fs, rounded)) { |
2118 set_fpu_register(fd_reg, kFPUInvalidResult); | 2421 set_fpu_register(fd_reg, kFPUInvalidResult); |
2119 } | 2422 } |
2120 } | 2423 } |
2121 break; | 2424 break; |
2122 case TRUNC_W_D: // Truncate double to word (round towards 0). | 2425 case TRUNC_W_D: // Truncate double to word (round towards 0). |
2123 { | 2426 { |
2124 double rounded = trunc(fs); | 2427 double rounded = trunc(fs); |
2125 int32_t result = static_cast<int32_t>(rounded); | 2428 int32_t result = static_cast<int32_t>(rounded); |
2126 set_fpu_register(fd_reg, result); | 2429 set_fpu_register_word(fd_reg, result); |
2127 if (set_fcsr_round_error(fs, rounded)) { | 2430 if (set_fcsr_round_error(fs, rounded)) { |
2128 set_fpu_register(fd_reg, kFPUInvalidResult); | 2431 set_fpu_register(fd_reg, kFPUInvalidResult); |
2129 } | 2432 } |
2130 } | 2433 } |
2131 break; | 2434 break; |
2132 case FLOOR_W_D: // Round double to word towards negative infinity. | 2435 case FLOOR_W_D: // Round double to word towards negative infinity. |
2133 { | 2436 { |
2134 double rounded = std::floor(fs); | 2437 double rounded = std::floor(fs); |
2135 int32_t result = static_cast<int32_t>(rounded); | 2438 int32_t result = static_cast<int32_t>(rounded); |
2136 set_fpu_register(fd_reg, result); | 2439 set_fpu_register_word(fd_reg, result); |
2137 if (set_fcsr_round_error(fs, rounded)) { | 2440 if (set_fcsr_round_error(fs, rounded)) { |
2138 set_fpu_register(fd_reg, kFPUInvalidResult); | 2441 set_fpu_register(fd_reg, kFPUInvalidResult); |
2139 } | 2442 } |
2140 } | 2443 } |
2141 break; | 2444 break; |
2142 case CEIL_W_D: // Round double to word towards positive infinity. | 2445 case CEIL_W_D: // Round double to word towards positive infinity. |
2143 { | 2446 { |
2144 double rounded = std::ceil(fs); | 2447 double rounded = std::ceil(fs); |
2145 int32_t result = static_cast<int32_t>(rounded); | 2448 int32_t result = static_cast<int32_t>(rounded); |
2146 set_fpu_register(fd_reg, result); | 2449 set_fpu_register_word(fd_reg, result); |
2147 if (set_fcsr_round_error(fs, rounded)) { | 2450 if (set_fcsr_round_error(fs, rounded)) { |
2148 set_fpu_register(fd_reg, kFPUInvalidResult); | 2451 set_fpu_register(fd_reg, kFPUInvalidResult); |
2149 } | 2452 } |
2150 } | 2453 } |
2151 break; | 2454 break; |
2152 case CVT_S_D: // Convert double to float (single). | 2455 case CVT_S_D: // Convert double to float (single). |
2153 set_fpu_register_float(fd_reg, static_cast<float>(fs)); | 2456 set_fpu_register_float(fd_reg, static_cast<float>(fs)); |
2154 break; | 2457 break; |
2155 case CVT_L_D: { // Mips32r2: Truncate double to 64-bit long-word. | 2458 case CVT_L_D: // Mips64r2: Truncate double to 64-bit long-word. |
2156 double rounded = trunc(fs); | 2459 // Rounding modes are not yet supported. |
2157 i64 = static_cast<int64_t>(rounded); | 2460 ASSERT((FCSR_ & 3) == 0); |
2158 set_fpu_register(fd_reg, i64 & 0xffffffff); | 2461 // In rounding mode 0 it should behave like ROUND. |
2159 set_fpu_register(fd_reg + 1, i64 >> 32); | 2462 // No break. |
| 2463 case ROUND_L_D: { // Mips64r2 instruction. |
| 2464 // check error cases |
| 2465 double rounded = fs > 0 ? floor(fs + 0.5) : ceil(fs - 0.5); |
| 2466 int64_t result = static_cast<int64_t>(rounded); |
| 2467 set_fpu_register(fd_reg, result); |
| 2468 if (set_fcsr_round64_error(fs, rounded)) { |
| 2469 set_fpu_register(fd_reg, kFPU64InvalidResult); |
| 2470 } |
2160 break; | 2471 break; |
2161 } | 2472 } |
2162 case TRUNC_L_D: { // Mips32r2 instruction. | 2473 case TRUNC_L_D: { // Mips64r2 instruction. |
2163 double rounded = trunc(fs); | 2474 double rounded = trunc(fs); |
2164 i64 = static_cast<int64_t>(rounded); | 2475 int64_t result = static_cast<int64_t>(rounded); |
2165 set_fpu_register(fd_reg, i64 & 0xffffffff); | 2476 set_fpu_register(fd_reg, result); |
2166 set_fpu_register(fd_reg + 1, i64 >> 32); | 2477 if (set_fcsr_round64_error(fs, rounded)) { |
| 2478 set_fpu_register(fd_reg, kFPU64InvalidResult); |
| 2479 } |
2167 break; | 2480 break; |
2168 } | 2481 } |
2169 case ROUND_L_D: { // Mips32r2 instruction. | 2482 case FLOOR_L_D: { // Mips64r2 instruction. |
2170 double rounded = | 2483 double rounded = floor(fs); |
2171 fs > 0 ? std::floor(fs + 0.5) : std::ceil(fs - 0.5); | 2484 int64_t result = static_cast<int64_t>(rounded); |
2172 i64 = static_cast<int64_t>(rounded); | 2485 set_fpu_register(fd_reg, result); |
2173 set_fpu_register(fd_reg, i64 & 0xffffffff); | 2486 if (set_fcsr_round64_error(fs, rounded)) { |
2174 set_fpu_register(fd_reg + 1, i64 >> 32); | 2487 set_fpu_register(fd_reg, kFPU64InvalidResult); |
| 2488 } |
2175 break; | 2489 break; |
2176 } | 2490 } |
2177 case FLOOR_L_D: // Mips32r2 instruction. | 2491 case CEIL_L_D: { // Mips64r2 instruction. |
2178 i64 = static_cast<int64_t>(std::floor(fs)); | 2492 double rounded = ceil(fs); |
2179 set_fpu_register(fd_reg, i64 & 0xffffffff); | 2493 int64_t result = static_cast<int64_t>(rounded); |
2180 set_fpu_register(fd_reg + 1, i64 >> 32); | 2494 set_fpu_register(fd_reg, result); |
| 2495 if (set_fcsr_round64_error(fs, rounded)) { |
| 2496 set_fpu_register(fd_reg, kFPU64InvalidResult); |
| 2497 } |
2181 break; | 2498 break; |
2182 case CEIL_L_D: // Mips32r2 instruction. | 2499 } |
2183 i64 = static_cast<int64_t>(std::ceil(fs)); | |
2184 set_fpu_register(fd_reg, i64 & 0xffffffff); | |
2185 set_fpu_register(fd_reg + 1, i64 >> 32); | |
2186 break; | |
2187 case C_F_D: | 2500 case C_F_D: |
2188 UNIMPLEMENTED_MIPS(); | 2501 UNIMPLEMENTED_MIPS(); |
2189 break; | 2502 break; |
2190 default: | 2503 default: |
2191 UNREACHABLE(); | 2504 UNREACHABLE(); |
2192 } | 2505 } |
2193 break; | 2506 break; |
2194 case W: | 2507 case W: |
2195 switch (instr->FunctionFieldRaw()) { | 2508 switch (instr->FunctionFieldRaw()) { |
2196 case CVT_S_W: // Convert word to float (single). | 2509 case CVT_S_W: // Convert word to float (single). |
2197 alu_out = get_fpu_register(fs_reg); | 2510 alu_out = get_fpu_register_signed_word(fs_reg); |
2198 set_fpu_register_float(fd_reg, static_cast<float>(alu_out)); | 2511 set_fpu_register_float(fd_reg, static_cast<float>(alu_out)); |
2199 break; | 2512 break; |
2200 case CVT_D_W: // Convert word to double. | 2513 case CVT_D_W: // Convert word to double. |
2201 alu_out = get_fpu_register(fs_reg); | 2514 alu_out = get_fpu_register_signed_word(fs_reg); |
2202 set_fpu_register_double(fd_reg, static_cast<double>(alu_out)); | 2515 set_fpu_register_double(fd_reg, static_cast<double>(alu_out)); |
2203 break; | 2516 break; |
2204 default: | 2517 default: |
2205 UNREACHABLE(); | 2518 UNREACHABLE(); |
2206 } | 2519 } |
2207 break; | 2520 break; |
2208 case L: | 2521 case L: |
2209 switch (instr->FunctionFieldRaw()) { | 2522 switch (instr->FunctionFieldRaw()) { |
2210 case CVT_D_L: // Mips32r2 instruction. | 2523 case CVT_D_L: // Mips32r2 instruction. |
2211 // Watch the signs here, we want 2 32-bit vals | 2524 i64 = get_fpu_register(fs_reg); |
2212 // to make a sign-64. | |
2213 i64 = static_cast<uint32_t>(get_fpu_register(fs_reg)); | |
2214 i64 |= static_cast<int64_t>(get_fpu_register(fs_reg + 1)) << 32; | |
2215 set_fpu_register_double(fd_reg, static_cast<double>(i64)); | 2525 set_fpu_register_double(fd_reg, static_cast<double>(i64)); |
2216 break; | 2526 break; |
2217 case CVT_S_L: | 2527 case CVT_S_L: |
2218 UNIMPLEMENTED_MIPS(); | 2528 UNIMPLEMENTED_MIPS(); |
2219 break; | 2529 break; |
2220 default: | 2530 default: |
2221 UNREACHABLE(); | 2531 UNREACHABLE(); |
2222 } | 2532 } |
2223 break; | 2533 break; |
2224 case PS: | 2534 case PS: |
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2262 } | 2572 } |
2263 // Instructions using HI and LO registers. | 2573 // Instructions using HI and LO registers. |
2264 case MULT: | 2574 case MULT: |
2265 set_register(LO, static_cast<int32_t>(i64hilo & 0xffffffff)); | 2575 set_register(LO, static_cast<int32_t>(i64hilo & 0xffffffff)); |
2266 set_register(HI, static_cast<int32_t>(i64hilo >> 32)); | 2576 set_register(HI, static_cast<int32_t>(i64hilo >> 32)); |
2267 break; | 2577 break; |
2268 case MULTU: | 2578 case MULTU: |
2269 set_register(LO, static_cast<int32_t>(u64hilo & 0xffffffff)); | 2579 set_register(LO, static_cast<int32_t>(u64hilo & 0xffffffff)); |
2270 set_register(HI, static_cast<int32_t>(u64hilo >> 32)); | 2580 set_register(HI, static_cast<int32_t>(u64hilo >> 32)); |
2271 break; | 2581 break; |
| 2582 case DMULT: |
| 2583 set_register(LO, static_cast<int64_t>(i128resultL)); |
| 2584 set_register(HI, static_cast<int64_t>(i128resultH)); |
| 2585 break; |
| 2586 case DMULTU: |
| 2587 UNIMPLEMENTED_MIPS(); |
| 2588 break; |
2272 case DIV: | 2589 case DIV: |
| 2590 case DDIV: |
2273 // Divide by zero and overflow was not checked in the configuration | 2591 // Divide by zero and overflow was not checked in the configuration |
2274 // step - div and divu do not raise exceptions. On division by 0 | 2592 // step - div and divu do not raise exceptions. On division by 0 |
2275 // the result will be UNPREDICTABLE. On overflow (INT_MIN/-1), | 2593 // the result will be UNPREDICTABLE. On overflow (INT_MIN/-1), |
2276 // return INT_MIN which is what the hardware does. | 2594 // return INT_MIN which is what the hardware does. |
2277 if (rs == INT_MIN && rt == -1) { | 2595 if (rs == INT_MIN && rt == -1) { |
2278 set_register(LO, INT_MIN); | 2596 set_register(LO, INT_MIN); |
2279 set_register(HI, 0); | 2597 set_register(HI, 0); |
2280 } else if (rt != 0) { | 2598 } else if (rt != 0) { |
2281 set_register(LO, rs / rt); | 2599 set_register(LO, rs / rt); |
2282 set_register(HI, rs % rt); | 2600 set_register(HI, rs % rt); |
(...skipping 12 matching lines...) Expand all Loading... |
2295 case TLT: | 2613 case TLT: |
2296 case TLTU: | 2614 case TLTU: |
2297 case TEQ: | 2615 case TEQ: |
2298 case TNE: | 2616 case TNE: |
2299 if (do_interrupt) { | 2617 if (do_interrupt) { |
2300 SoftwareInterrupt(instr); | 2618 SoftwareInterrupt(instr); |
2301 } | 2619 } |
2302 break; | 2620 break; |
2303 // Conditional moves. | 2621 // Conditional moves. |
2304 case MOVN: | 2622 case MOVN: |
2305 if (rt) set_register(rd_reg, rs); | 2623 if (rt) { |
| 2624 set_register(rd_reg, rs); |
| 2625 TraceRegWr(rs); |
| 2626 } |
2306 break; | 2627 break; |
2307 case MOVCI: { | 2628 case MOVCI: { |
2308 uint32_t cc = instr->FBccValue(); | 2629 uint32_t cc = instr->FBccValue(); |
2309 uint32_t fcsr_cc = get_fcsr_condition_bit(cc); | 2630 uint32_t fcsr_cc = get_fcsr_condition_bit(cc); |
2310 if (instr->Bit(16)) { // Read Tf bit. | 2631 if (instr->Bit(16)) { // Read Tf bit. |
2311 if (test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs); | 2632 if (test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs); |
2312 } else { | 2633 } else { |
2313 if (!test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs); | 2634 if (!test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs); |
2314 } | 2635 } |
2315 break; | 2636 break; |
2316 } | 2637 } |
2317 case MOVZ: | 2638 case MOVZ: |
2318 if (!rt) set_register(rd_reg, rs); | 2639 if (!rt) { |
| 2640 set_register(rd_reg, rs); |
| 2641 TraceRegWr(rs); |
| 2642 } |
2319 break; | 2643 break; |
2320 default: // For other special opcodes we do the default operation. | 2644 default: // For other special opcodes we do the default operation. |
2321 set_register(rd_reg, alu_out); | 2645 set_register(rd_reg, alu_out); |
| 2646 TraceRegWr(alu_out); |
2322 } | 2647 } |
2323 break; | 2648 break; |
2324 case SPECIAL2: | 2649 case SPECIAL2: |
2325 switch (instr->FunctionFieldRaw()) { | 2650 switch (instr->FunctionFieldRaw()) { |
2326 case MUL: | 2651 case MUL: |
2327 set_register(rd_reg, alu_out); | 2652 set_register(rd_reg, alu_out); |
| 2653 TraceRegWr(alu_out); |
2328 // HI and LO are UNPREDICTABLE after the operation. | 2654 // HI and LO are UNPREDICTABLE after the operation. |
2329 set_register(LO, Unpredictable); | 2655 set_register(LO, Unpredictable); |
2330 set_register(HI, Unpredictable); | 2656 set_register(HI, Unpredictable); |
2331 break; | 2657 break; |
2332 default: // For other special2 opcodes we do the default operation. | 2658 default: // For other special2 opcodes we do the default operation. |
2333 set_register(rd_reg, alu_out); | 2659 set_register(rd_reg, alu_out); |
2334 } | 2660 } |
2335 break; | 2661 break; |
2336 case SPECIAL3: | 2662 case SPECIAL3: |
2337 switch (instr->FunctionFieldRaw()) { | 2663 switch (instr->FunctionFieldRaw()) { |
2338 case INS: | 2664 case INS: |
2339 // Ins instr leaves result in Rt, rather than Rd. | 2665 // Ins instr leaves result in Rt, rather than Rd. |
2340 set_register(rt_reg, alu_out); | 2666 set_register(rt_reg, alu_out); |
| 2667 TraceRegWr(alu_out); |
2341 break; | 2668 break; |
2342 case EXT: | 2669 case EXT: |
2343 // Ext instr leaves result in Rt, rather than Rd. | 2670 // Ext instr leaves result in Rt, rather than Rd. |
2344 set_register(rt_reg, alu_out); | 2671 set_register(rt_reg, alu_out); |
| 2672 TraceRegWr(alu_out); |
2345 break; | 2673 break; |
2346 default: | 2674 default: |
2347 UNREACHABLE(); | 2675 UNREACHABLE(); |
2348 } | 2676 } |
2349 break; | 2677 break; |
2350 // Unimplemented opcodes raised an error in the configuration step before, | 2678 // Unimplemented opcodes raised an error in the configuration step before, |
2351 // so we can use the default here to set the destination register in common | 2679 // so we can use the default here to set the destination register in common |
2352 // cases. | 2680 // cases. |
2353 default: | 2681 default: |
2354 set_register(rd_reg, alu_out); | 2682 set_register(rd_reg, alu_out); |
| 2683 TraceRegWr(alu_out); |
2355 } | 2684 } |
2356 } | 2685 } |
2357 | 2686 |
2358 | 2687 |
2359 // Type 2: instructions using a 16 bytes immediate. (e.g. addi, beq). | 2688 // Type 2: instructions using a 16 bytes immediate. (e.g. addi, beq). |
2360 void Simulator::DecodeTypeImmediate(Instruction* instr) { | 2689 void Simulator::DecodeTypeImmediate(Instruction* instr) { |
2361 // Instruction fields. | 2690 // Instruction fields. |
2362 Opcode op = instr->OpcodeFieldRaw(); | 2691 Opcode op = instr->OpcodeFieldRaw(); |
2363 int32_t rs = get_register(instr->RsValue()); | 2692 int64_t rs = get_register(instr->RsValue()); |
2364 uint32_t rs_u = static_cast<uint32_t>(rs); | 2693 uint64_t rs_u = static_cast<uint64_t>(rs); |
2365 int32_t rt_reg = instr->RtValue(); // Destination register. | 2694 int64_t rt_reg = instr->RtValue(); // Destination register. |
2366 int32_t rt = get_register(rt_reg); | 2695 int64_t rt = get_register(rt_reg); |
2367 int16_t imm16 = instr->Imm16Value(); | 2696 int16_t imm16 = instr->Imm16Value(); |
2368 | 2697 |
2369 int32_t ft_reg = instr->FtValue(); // Destination register. | 2698 int32_t ft_reg = instr->FtValue(); // Destination register. |
2370 | 2699 |
2371 // Zero extended immediate. | 2700 // Zero extended immediate. |
2372 uint32_t oe_imm16 = 0xffff & imm16; | 2701 uint32_t oe_imm16 = 0xffff & imm16; |
2373 // Sign extended immediate. | 2702 // Sign extended immediate. |
2374 int32_t se_imm16 = imm16; | 2703 int32_t se_imm16 = imm16; |
2375 | 2704 |
2376 // Get current pc. | 2705 // Get current pc. |
2377 int32_t current_pc = get_pc(); | 2706 int64_t current_pc = get_pc(); |
2378 // Next pc. | 2707 // Next pc. |
2379 int32_t next_pc = bad_ra; | 2708 int64_t next_pc = bad_ra; |
2380 | 2709 |
2381 // Used for conditional branch instructions. | 2710 // Used for conditional branch instructions. |
2382 bool do_branch = false; | 2711 bool do_branch = false; |
2383 bool execute_branch_delay_instruction = false; | 2712 bool execute_branch_delay_instruction = false; |
2384 | 2713 |
2385 // Used for arithmetic instructions. | 2714 // Used for arithmetic instructions. |
2386 int32_t alu_out = 0; | 2715 int64_t alu_out = 0; |
2387 // Floating point. | 2716 // Floating point. |
2388 double fp_out = 0.0; | 2717 double fp_out = 0.0; |
2389 uint32_t cc, cc_value, fcsr_cc; | 2718 uint32_t cc, cc_value, fcsr_cc; |
2390 | 2719 |
2391 // Used for memory instructions. | 2720 // Used for memory instructions. |
2392 int32_t addr = 0x0; | 2721 int64_t addr = 0x0; |
2393 // Value to be written in memory. | 2722 // Value to be written in memory. |
2394 uint32_t mem_value = 0x0; | 2723 uint64_t mem_value = 0x0; |
| 2724 // Alignment for 32-bit integers used in LWL, LWR, etc. |
| 2725 const int kInt32AlignmentMask = sizeof(uint32_t) - 1; |
2395 | 2726 |
2396 // ---------- Configuration (and execution for REGIMM). | 2727 // ---------- Configuration (and execution for REGIMM). |
2397 switch (op) { | 2728 switch (op) { |
2398 // ------------- COP1. Coprocessor instructions. | 2729 // ------------- COP1. Coprocessor instructions. |
2399 case COP1: | 2730 case COP1: |
2400 switch (instr->RsFieldRaw()) { | 2731 switch (instr->RsFieldRaw()) { |
2401 case BC1: // Branch on coprocessor condition. | 2732 case BC1: // Branch on coprocessor condition. |
2402 cc = instr->FBccValue(); | 2733 cc = instr->FBccValue(); |
2403 fcsr_cc = get_fcsr_condition_bit(cc); | 2734 fcsr_cc = get_fcsr_condition_bit(cc); |
2404 cc_value = test_fcsr_bit(fcsr_cc); | 2735 cc_value = test_fcsr_bit(fcsr_cc); |
(...skipping 58 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2463 do_branch = rs != rt; | 2794 do_branch = rs != rt; |
2464 break; | 2795 break; |
2465 case BLEZ: | 2796 case BLEZ: |
2466 do_branch = rs <= 0; | 2797 do_branch = rs <= 0; |
2467 break; | 2798 break; |
2468 case BGTZ: | 2799 case BGTZ: |
2469 do_branch = rs > 0; | 2800 do_branch = rs > 0; |
2470 break; | 2801 break; |
2471 // ------------- Arithmetic instructions. | 2802 // ------------- Arithmetic instructions. |
2472 case ADDI: | 2803 case ADDI: |
| 2804 case DADDI: |
2473 if (HaveSameSign(rs, se_imm16)) { | 2805 if (HaveSameSign(rs, se_imm16)) { |
2474 if (rs > 0) { | 2806 if (rs > 0) { |
2475 exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - se_imm16); | 2807 exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - se_imm16); |
2476 } else if (rs < 0) { | 2808 } else if (rs < 0) { |
2477 exceptions[kIntegerUnderflow] = | 2809 exceptions[kIntegerUnderflow] = |
2478 rs < (Registers::kMinValue - se_imm16); | 2810 rs < (Registers::kMinValue - se_imm16); |
2479 } | 2811 } |
2480 } | 2812 } |
2481 alu_out = rs + se_imm16; | 2813 alu_out = rs + se_imm16; |
2482 break; | 2814 break; |
2483 case ADDIU: | 2815 case ADDIU: { |
| 2816 int32_t alu32_out = rs + se_imm16; |
| 2817 // Sign-extend result of 32bit operation into 64bit register. |
| 2818 alu_out = static_cast<int64_t>(alu32_out); |
| 2819 } |
| 2820 break; |
| 2821 case DADDIU: |
2484 alu_out = rs + se_imm16; | 2822 alu_out = rs + se_imm16; |
2485 break; | 2823 break; |
2486 case SLTI: | 2824 case SLTI: |
2487 alu_out = (rs < se_imm16) ? 1 : 0; | 2825 alu_out = (rs < se_imm16) ? 1 : 0; |
2488 break; | 2826 break; |
2489 case SLTIU: | 2827 case SLTIU: |
2490 alu_out = (rs_u < static_cast<uint32_t>(se_imm16)) ? 1 : 0; | 2828 alu_out = (rs_u < static_cast<uint32_t>(se_imm16)) ? 1 : 0; |
2491 break; | 2829 break; |
2492 case ANDI: | 2830 case ANDI: |
2493 alu_out = rs & oe_imm16; | 2831 alu_out = rs & oe_imm16; |
2494 break; | 2832 break; |
2495 case ORI: | 2833 case ORI: |
2496 alu_out = rs | oe_imm16; | 2834 alu_out = rs | oe_imm16; |
2497 break; | 2835 break; |
2498 case XORI: | 2836 case XORI: |
2499 alu_out = rs ^ oe_imm16; | 2837 alu_out = rs ^ oe_imm16; |
2500 break; | 2838 break; |
2501 case LUI: | 2839 case LUI: { |
2502 alu_out = (oe_imm16 << 16); | 2840 int32_t alu32_out = (oe_imm16 << 16); |
| 2841 // Sign-extend result of 32bit operation into 64bit register. |
| 2842 alu_out = static_cast<int64_t>(alu32_out); |
| 2843 } |
2503 break; | 2844 break; |
2504 // ------------- Memory instructions. | 2845 // ------------- Memory instructions. |
2505 case LB: | 2846 case LB: |
2506 addr = rs + se_imm16; | 2847 addr = rs + se_imm16; |
2507 alu_out = ReadB(addr); | 2848 alu_out = ReadB(addr); |
2508 break; | 2849 break; |
2509 case LH: | 2850 case LH: |
2510 addr = rs + se_imm16; | 2851 addr = rs + se_imm16; |
2511 alu_out = ReadH(addr, instr); | 2852 alu_out = ReadH(addr, instr); |
2512 break; | 2853 break; |
2513 case LWL: { | 2854 case LWL: { |
2514 // al_offset is offset of the effective address within an aligned word. | 2855 // al_offset is offset of the effective address within an aligned word. |
2515 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; | 2856 uint8_t al_offset = (rs + se_imm16) & kInt32AlignmentMask; |
2516 uint8_t byte_shift = kPointerAlignmentMask - al_offset; | 2857 uint8_t byte_shift = kInt32AlignmentMask - al_offset; |
2517 uint32_t mask = (1 << byte_shift * 8) - 1; | 2858 uint32_t mask = (1 << byte_shift * 8) - 1; |
2518 addr = rs + se_imm16 - al_offset; | 2859 addr = rs + se_imm16 - al_offset; |
2519 alu_out = ReadW(addr, instr); | 2860 alu_out = ReadW(addr, instr); |
2520 alu_out <<= byte_shift * 8; | 2861 alu_out <<= byte_shift * 8; |
2521 alu_out |= rt & mask; | 2862 alu_out |= rt & mask; |
2522 break; | 2863 break; |
2523 } | 2864 } |
2524 case LW: | 2865 case LW: |
2525 addr = rs + se_imm16; | 2866 addr = rs + se_imm16; |
2526 alu_out = ReadW(addr, instr); | 2867 alu_out = ReadW(addr, instr); |
2527 break; | 2868 break; |
| 2869 case LWU: |
| 2870 addr = rs + se_imm16; |
| 2871 alu_out = ReadWU(addr, instr); |
| 2872 break; |
| 2873 case LD: |
| 2874 addr = rs + se_imm16; |
| 2875 alu_out = Read2W(addr, instr); |
| 2876 break; |
2528 case LBU: | 2877 case LBU: |
2529 addr = rs + se_imm16; | 2878 addr = rs + se_imm16; |
2530 alu_out = ReadBU(addr); | 2879 alu_out = ReadBU(addr); |
2531 break; | 2880 break; |
2532 case LHU: | 2881 case LHU: |
2533 addr = rs + se_imm16; | 2882 addr = rs + se_imm16; |
2534 alu_out = ReadHU(addr, instr); | 2883 alu_out = ReadHU(addr, instr); |
2535 break; | 2884 break; |
2536 case LWR: { | 2885 case LWR: { |
2537 // al_offset is offset of the effective address within an aligned word. | 2886 // al_offset is offset of the effective address within an aligned word. |
2538 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; | 2887 uint8_t al_offset = (rs + se_imm16) & kInt32AlignmentMask; |
2539 uint8_t byte_shift = kPointerAlignmentMask - al_offset; | 2888 uint8_t byte_shift = kInt32AlignmentMask - al_offset; |
2540 uint32_t mask = al_offset ? (~0 << (byte_shift + 1) * 8) : 0; | 2889 uint32_t mask = al_offset ? (~0 << (byte_shift + 1) * 8) : 0; |
2541 addr = rs + se_imm16 - al_offset; | 2890 addr = rs + se_imm16 - al_offset; |
2542 alu_out = ReadW(addr, instr); | 2891 alu_out = ReadW(addr, instr); |
2543 alu_out = static_cast<uint32_t> (alu_out) >> al_offset * 8; | 2892 alu_out = static_cast<uint32_t> (alu_out) >> al_offset * 8; |
2544 alu_out |= rt & mask; | 2893 alu_out |= rt & mask; |
2545 break; | 2894 break; |
2546 } | 2895 } |
2547 case SB: | 2896 case SB: |
2548 addr = rs + se_imm16; | 2897 addr = rs + se_imm16; |
2549 break; | 2898 break; |
2550 case SH: | 2899 case SH: |
2551 addr = rs + se_imm16; | 2900 addr = rs + se_imm16; |
2552 break; | 2901 break; |
2553 case SWL: { | 2902 case SWL: { |
2554 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; | 2903 uint8_t al_offset = (rs + se_imm16) & kInt32AlignmentMask; |
2555 uint8_t byte_shift = kPointerAlignmentMask - al_offset; | 2904 uint8_t byte_shift = kInt32AlignmentMask - al_offset; |
2556 uint32_t mask = byte_shift ? (~0 << (al_offset + 1) * 8) : 0; | 2905 uint32_t mask = byte_shift ? (~0 << (al_offset + 1) * 8) : 0; |
2557 addr = rs + se_imm16 - al_offset; | 2906 addr = rs + se_imm16 - al_offset; |
2558 mem_value = ReadW(addr, instr) & mask; | 2907 mem_value = ReadW(addr, instr) & mask; |
2559 mem_value |= static_cast<uint32_t>(rt) >> byte_shift * 8; | 2908 mem_value |= static_cast<uint32_t>(rt) >> byte_shift * 8; |
2560 break; | 2909 break; |
2561 } | 2910 } |
2562 case SW: | 2911 case SW: |
| 2912 case SD: |
2563 addr = rs + se_imm16; | 2913 addr = rs + se_imm16; |
2564 break; | 2914 break; |
2565 case SWR: { | 2915 case SWR: { |
2566 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; | 2916 uint8_t al_offset = (rs + se_imm16) & kInt32AlignmentMask; |
2567 uint32_t mask = (1 << al_offset * 8) - 1; | 2917 uint32_t mask = (1 << al_offset * 8) - 1; |
2568 addr = rs + se_imm16 - al_offset; | 2918 addr = rs + se_imm16 - al_offset; |
2569 mem_value = ReadW(addr, instr); | 2919 mem_value = ReadW(addr, instr); |
2570 mem_value = (rt << al_offset * 8) | (mem_value & mask); | 2920 mem_value = (rt << al_offset * 8) | (mem_value & mask); |
2571 break; | 2921 break; |
2572 } | 2922 } |
2573 case LWC1: | 2923 case LWC1: |
2574 addr = rs + se_imm16; | 2924 addr = rs + se_imm16; |
2575 alu_out = ReadW(addr, instr); | 2925 alu_out = ReadW(addr, instr); |
2576 break; | 2926 break; |
(...skipping 26 matching lines...) Expand all Loading... |
2603 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; | 2953 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; |
2604 if (instr->IsLinkingInstruction()) { | 2954 if (instr->IsLinkingInstruction()) { |
2605 set_register(31, current_pc + 2* Instruction::kInstrSize); | 2955 set_register(31, current_pc + 2* Instruction::kInstrSize); |
2606 } | 2956 } |
2607 } else { | 2957 } else { |
2608 next_pc = current_pc + 2 * Instruction::kInstrSize; | 2958 next_pc = current_pc + 2 * Instruction::kInstrSize; |
2609 } | 2959 } |
2610 break; | 2960 break; |
2611 // ------------- Arithmetic instructions. | 2961 // ------------- Arithmetic instructions. |
2612 case ADDI: | 2962 case ADDI: |
| 2963 case DADDI: |
2613 case ADDIU: | 2964 case ADDIU: |
| 2965 case DADDIU: |
2614 case SLTI: | 2966 case SLTI: |
2615 case SLTIU: | 2967 case SLTIU: |
2616 case ANDI: | 2968 case ANDI: |
2617 case ORI: | 2969 case ORI: |
2618 case XORI: | 2970 case XORI: |
2619 case LUI: | 2971 case LUI: |
2620 set_register(rt_reg, alu_out); | 2972 set_register(rt_reg, alu_out); |
| 2973 TraceRegWr(alu_out); |
2621 break; | 2974 break; |
2622 // ------------- Memory instructions. | 2975 // ------------- Memory instructions. |
2623 case LB: | 2976 case LB: |
2624 case LH: | 2977 case LH: |
2625 case LWL: | 2978 case LWL: |
2626 case LW: | 2979 case LW: |
| 2980 case LWU: |
| 2981 case LD: |
2627 case LBU: | 2982 case LBU: |
2628 case LHU: | 2983 case LHU: |
2629 case LWR: | 2984 case LWR: |
2630 set_register(rt_reg, alu_out); | 2985 set_register(rt_reg, alu_out); |
2631 break; | 2986 break; |
2632 case SB: | 2987 case SB: |
2633 WriteB(addr, static_cast<int8_t>(rt)); | 2988 WriteB(addr, static_cast<int8_t>(rt)); |
2634 break; | 2989 break; |
2635 case SH: | 2990 case SH: |
2636 WriteH(addr, static_cast<uint16_t>(rt), instr); | 2991 WriteH(addr, static_cast<uint16_t>(rt), instr); |
2637 break; | 2992 break; |
2638 case SWL: | 2993 case SWL: |
2639 WriteW(addr, mem_value, instr); | 2994 WriteW(addr, mem_value, instr); |
2640 break; | 2995 break; |
2641 case SW: | 2996 case SW: |
2642 WriteW(addr, rt, instr); | 2997 WriteW(addr, rt, instr); |
2643 break; | 2998 break; |
| 2999 case SD: |
| 3000 Write2W(addr, rt, instr); |
| 3001 break; |
2644 case SWR: | 3002 case SWR: |
2645 WriteW(addr, mem_value, instr); | 3003 WriteW(addr, mem_value, instr); |
2646 break; | 3004 break; |
2647 case LWC1: | 3005 case LWC1: |
2648 set_fpu_register(ft_reg, alu_out); | 3006 set_fpu_register(ft_reg, kFPUInvalidResult); // Trash upper 32 bits. |
| 3007 set_fpu_register_word(ft_reg, static_cast<int32_t>(alu_out)); |
2649 break; | 3008 break; |
2650 case LDC1: | 3009 case LDC1: |
2651 set_fpu_register_double(ft_reg, fp_out); | 3010 set_fpu_register_double(ft_reg, fp_out); |
2652 break; | 3011 break; |
2653 case SWC1: | 3012 case SWC1: |
2654 addr = rs + se_imm16; | 3013 addr = rs + se_imm16; |
2655 WriteW(addr, get_fpu_register(ft_reg), instr); | 3014 WriteW(addr, get_fpu_register(ft_reg), instr); |
2656 break; | 3015 break; |
2657 case SDC1: | 3016 case SDC1: |
2658 addr = rs + se_imm16; | 3017 addr = rs + se_imm16; |
(...skipping 45 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2704 pc_modified_ = true; | 3063 pc_modified_ = true; |
2705 } | 3064 } |
2706 | 3065 |
2707 | 3066 |
2708 // Executes the current instruction. | 3067 // Executes the current instruction. |
2709 void Simulator::InstructionDecode(Instruction* instr) { | 3068 void Simulator::InstructionDecode(Instruction* instr) { |
2710 if (v8::internal::FLAG_check_icache) { | 3069 if (v8::internal::FLAG_check_icache) { |
2711 CheckICache(isolate_->simulator_i_cache(), instr); | 3070 CheckICache(isolate_->simulator_i_cache(), instr); |
2712 } | 3071 } |
2713 pc_modified_ = false; | 3072 pc_modified_ = false; |
| 3073 |
| 3074 v8::internal::EmbeddedVector<char, 256> buffer; |
| 3075 |
2714 if (::v8::internal::FLAG_trace_sim) { | 3076 if (::v8::internal::FLAG_trace_sim) { |
| 3077 SNPrintF(trace_buf_, " "); |
2715 disasm::NameConverter converter; | 3078 disasm::NameConverter converter; |
2716 disasm::Disassembler dasm(converter); | 3079 disasm::Disassembler dasm(converter); |
2717 // Use a reasonably large buffer. | 3080 // Use a reasonably large buffer. |
2718 v8::internal::EmbeddedVector<char, 256> buffer; | |
2719 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(instr)); | 3081 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(instr)); |
2720 PrintF(" 0x%08x %s\n", reinterpret_cast<intptr_t>(instr), | |
2721 buffer.start()); | |
2722 } | 3082 } |
2723 | 3083 |
2724 switch (instr->InstructionType()) { | 3084 switch (instr->InstructionType()) { |
2725 case Instruction::kRegisterType: | 3085 case Instruction::kRegisterType: |
2726 DecodeTypeRegister(instr); | 3086 DecodeTypeRegister(instr); |
2727 break; | 3087 break; |
2728 case Instruction::kImmediateType: | 3088 case Instruction::kImmediateType: |
2729 DecodeTypeImmediate(instr); | 3089 DecodeTypeImmediate(instr); |
2730 break; | 3090 break; |
2731 case Instruction::kJumpType: | 3091 case Instruction::kJumpType: |
2732 DecodeTypeJump(instr); | 3092 DecodeTypeJump(instr); |
2733 break; | 3093 break; |
2734 default: | 3094 default: |
2735 UNSUPPORTED(); | 3095 UNSUPPORTED(); |
2736 } | 3096 } |
| 3097 |
| 3098 if (::v8::internal::FLAG_trace_sim) { |
| 3099 PrintF(" 0x%08lx %-44s %s\n", reinterpret_cast<intptr_t>(instr), |
| 3100 buffer.start(), trace_buf_.start()); |
| 3101 } |
| 3102 |
2737 if (!pc_modified_) { | 3103 if (!pc_modified_) { |
2738 set_register(pc, reinterpret_cast<int32_t>(instr) + | 3104 set_register(pc, reinterpret_cast<int64_t>(instr) + |
2739 Instruction::kInstrSize); | 3105 Instruction::kInstrSize); |
2740 } | 3106 } |
2741 } | 3107 } |
2742 | 3108 |
2743 | 3109 |
2744 | 3110 |
2745 void Simulator::Execute() { | 3111 void Simulator::Execute() { |
2746 // Get the PC to simulate. Cannot use the accessor here as we need the | 3112 // Get the PC to simulate. Cannot use the accessor here as we need the |
2747 // raw PC value and not the one used as input to arithmetic instructions. | 3113 // raw PC value and not the one used as input to arithmetic instructions. |
2748 int program_counter = get_pc(); | 3114 int64_t program_counter = get_pc(); |
2749 if (::v8::internal::FLAG_stop_sim_at == 0) { | 3115 if (::v8::internal::FLAG_stop_sim_at == 0) { |
2750 // Fast version of the dispatch loop without checking whether the simulator | 3116 // Fast version of the dispatch loop without checking whether the simulator |
2751 // should be stopping at a particular executed instruction. | 3117 // should be stopping at a particular executed instruction. |
2752 while (program_counter != end_sim_pc) { | 3118 while (program_counter != end_sim_pc) { |
2753 Instruction* instr = reinterpret_cast<Instruction*>(program_counter); | 3119 Instruction* instr = reinterpret_cast<Instruction*>(program_counter); |
2754 icount_++; | 3120 icount_++; |
2755 InstructionDecode(instr); | 3121 InstructionDecode(instr); |
2756 program_counter = get_pc(); | 3122 program_counter = get_pc(); |
2757 } | 3123 } |
2758 } else { | 3124 } else { |
2759 // FLAG_stop_sim_at is at the non-default value. Stop in the debugger when | 3125 // FLAG_stop_sim_at is at the non-default value. Stop in the debugger when |
2760 // we reach the particular instuction count. | 3126 // we reach the particular instuction count. |
2761 while (program_counter != end_sim_pc) { | 3127 while (program_counter != end_sim_pc) { |
2762 Instruction* instr = reinterpret_cast<Instruction*>(program_counter); | 3128 Instruction* instr = reinterpret_cast<Instruction*>(program_counter); |
2763 icount_++; | 3129 icount_++; |
2764 if (icount_ == ::v8::internal::FLAG_stop_sim_at) { | 3130 if (icount_ == static_cast<int64_t>(::v8::internal::FLAG_stop_sim_at)) { |
2765 MipsDebugger dbg(this); | 3131 MipsDebugger dbg(this); |
2766 dbg.Debug(); | 3132 dbg.Debug(); |
2767 } else { | 3133 } else { |
2768 InstructionDecode(instr); | 3134 InstructionDecode(instr); |
2769 } | 3135 } |
2770 program_counter = get_pc(); | 3136 program_counter = get_pc(); |
2771 } | 3137 } |
2772 } | 3138 } |
2773 } | 3139 } |
2774 | 3140 |
2775 | 3141 |
2776 void Simulator::CallInternal(byte* entry) { | 3142 void Simulator::CallInternal(byte* entry) { |
2777 // Prepare to execute the code at entry. | 3143 // Prepare to execute the code at entry. |
2778 set_register(pc, reinterpret_cast<int32_t>(entry)); | 3144 set_register(pc, reinterpret_cast<int64_t>(entry)); |
2779 // Put down marker for end of simulation. The simulator will stop simulation | 3145 // Put down marker for end of simulation. The simulator will stop simulation |
2780 // when the PC reaches this value. By saving the "end simulation" value into | 3146 // when the PC reaches this value. By saving the "end simulation" value into |
2781 // the LR the simulation stops when returning to this call point. | 3147 // the LR the simulation stops when returning to this call point. |
2782 set_register(ra, end_sim_pc); | 3148 set_register(ra, end_sim_pc); |
2783 | 3149 |
2784 // Remember the values of callee-saved registers. | 3150 // Remember the values of callee-saved registers. |
2785 // The code below assumes that r9 is not used as sb (static base) in | 3151 // The code below assumes that r9 is not used as sb (static base) in |
2786 // simulator code and therefore is regarded as a callee-saved register. | 3152 // simulator code and therefore is regarded as a callee-saved register. |
2787 int32_t s0_val = get_register(s0); | 3153 int64_t s0_val = get_register(s0); |
2788 int32_t s1_val = get_register(s1); | 3154 int64_t s1_val = get_register(s1); |
2789 int32_t s2_val = get_register(s2); | 3155 int64_t s2_val = get_register(s2); |
2790 int32_t s3_val = get_register(s3); | 3156 int64_t s3_val = get_register(s3); |
2791 int32_t s4_val = get_register(s4); | 3157 int64_t s4_val = get_register(s4); |
2792 int32_t s5_val = get_register(s5); | 3158 int64_t s5_val = get_register(s5); |
2793 int32_t s6_val = get_register(s6); | 3159 int64_t s6_val = get_register(s6); |
2794 int32_t s7_val = get_register(s7); | 3160 int64_t s7_val = get_register(s7); |
2795 int32_t gp_val = get_register(gp); | 3161 int64_t gp_val = get_register(gp); |
2796 int32_t sp_val = get_register(sp); | 3162 int64_t sp_val = get_register(sp); |
2797 int32_t fp_val = get_register(fp); | 3163 int64_t fp_val = get_register(fp); |
2798 | 3164 |
2799 // Set up the callee-saved registers with a known value. To be able to check | 3165 // Set up the callee-saved registers with a known value. To be able to check |
2800 // that they are preserved properly across JS execution. | 3166 // that they are preserved properly across JS execution. |
2801 int32_t callee_saved_value = icount_; | 3167 int64_t callee_saved_value = icount_; |
2802 set_register(s0, callee_saved_value); | 3168 set_register(s0, callee_saved_value); |
2803 set_register(s1, callee_saved_value); | 3169 set_register(s1, callee_saved_value); |
2804 set_register(s2, callee_saved_value); | 3170 set_register(s2, callee_saved_value); |
2805 set_register(s3, callee_saved_value); | 3171 set_register(s3, callee_saved_value); |
2806 set_register(s4, callee_saved_value); | 3172 set_register(s4, callee_saved_value); |
2807 set_register(s5, callee_saved_value); | 3173 set_register(s5, callee_saved_value); |
2808 set_register(s6, callee_saved_value); | 3174 set_register(s6, callee_saved_value); |
2809 set_register(s7, callee_saved_value); | 3175 set_register(s7, callee_saved_value); |
2810 set_register(gp, callee_saved_value); | 3176 set_register(gp, callee_saved_value); |
2811 set_register(fp, callee_saved_value); | 3177 set_register(fp, callee_saved_value); |
(...skipping 21 matching lines...) Expand all Loading... |
2833 set_register(s4, s4_val); | 3199 set_register(s4, s4_val); |
2834 set_register(s5, s5_val); | 3200 set_register(s5, s5_val); |
2835 set_register(s6, s6_val); | 3201 set_register(s6, s6_val); |
2836 set_register(s7, s7_val); | 3202 set_register(s7, s7_val); |
2837 set_register(gp, gp_val); | 3203 set_register(gp, gp_val); |
2838 set_register(sp, sp_val); | 3204 set_register(sp, sp_val); |
2839 set_register(fp, fp_val); | 3205 set_register(fp, fp_val); |
2840 } | 3206 } |
2841 | 3207 |
2842 | 3208 |
2843 int32_t Simulator::Call(byte* entry, int argument_count, ...) { | 3209 int64_t Simulator::Call(byte* entry, int argument_count, ...) { |
| 3210 const int kRegisterPassedArguments = (kMipsAbi == kN64) ? 8 : 4; |
2844 va_list parameters; | 3211 va_list parameters; |
2845 va_start(parameters, argument_count); | 3212 va_start(parameters, argument_count); |
2846 // Set up arguments. | 3213 // Set up arguments. |
2847 | 3214 |
2848 // First four arguments passed in registers. | 3215 // First four arguments passed in registers in both ABI's. |
2849 ASSERT(argument_count >= 4); | 3216 ASSERT(argument_count >= 4); |
2850 set_register(a0, va_arg(parameters, int32_t)); | 3217 set_register(a0, va_arg(parameters, int64_t)); |
2851 set_register(a1, va_arg(parameters, int32_t)); | 3218 set_register(a1, va_arg(parameters, int64_t)); |
2852 set_register(a2, va_arg(parameters, int32_t)); | 3219 set_register(a2, va_arg(parameters, int64_t)); |
2853 set_register(a3, va_arg(parameters, int32_t)); | 3220 set_register(a3, va_arg(parameters, int64_t)); |
| 3221 |
| 3222 if (kMipsAbi == kN64) { |
| 3223 // Up to eight arguments passed in registers in N64 ABI. |
| 3224 // TODO(plind): N64 ABI calls these regs a4 - a7. Clarify this. |
| 3225 if (argument_count >= 5) set_register(a4, va_arg(parameters, int64_t)); |
| 3226 if (argument_count >= 6) set_register(a5, va_arg(parameters, int64_t)); |
| 3227 if (argument_count >= 7) set_register(a6, va_arg(parameters, int64_t)); |
| 3228 if (argument_count >= 8) set_register(a7, va_arg(parameters, int64_t)); |
| 3229 } |
2854 | 3230 |
2855 // Remaining arguments passed on stack. | 3231 // Remaining arguments passed on stack. |
2856 int original_stack = get_register(sp); | 3232 int64_t original_stack = get_register(sp); |
2857 // Compute position of stack on entry to generated code. | 3233 // Compute position of stack on entry to generated code. |
2858 int entry_stack = (original_stack - (argument_count - 4) * sizeof(int32_t) | 3234 int stack_args_count = (argument_count > kRegisterPassedArguments) ? |
2859 - kCArgsSlotsSize); | 3235 (argument_count - kRegisterPassedArguments) : 0; |
| 3236 int stack_args_size = stack_args_count * sizeof(int64_t) + kCArgsSlotsSize; |
| 3237 int64_t entry_stack = original_stack - stack_args_size; |
| 3238 |
2860 if (base::OS::ActivationFrameAlignment() != 0) { | 3239 if (base::OS::ActivationFrameAlignment() != 0) { |
2861 entry_stack &= -base::OS::ActivationFrameAlignment(); | 3240 entry_stack &= -base::OS::ActivationFrameAlignment(); |
2862 } | 3241 } |
2863 // Store remaining arguments on stack, from low to high memory. | 3242 // Store remaining arguments on stack, from low to high memory. |
2864 intptr_t* stack_argument = reinterpret_cast<intptr_t*>(entry_stack); | 3243 intptr_t* stack_argument = reinterpret_cast<intptr_t*>(entry_stack); |
2865 for (int i = 4; i < argument_count; i++) { | 3244 for (int i = kRegisterPassedArguments; i < argument_count; i++) { |
2866 stack_argument[i - 4 + kCArgSlotCount] = va_arg(parameters, int32_t); | 3245 int stack_index = i - kRegisterPassedArguments + kCArgSlotCount; |
| 3246 stack_argument[stack_index] = va_arg(parameters, int64_t); |
2867 } | 3247 } |
2868 va_end(parameters); | 3248 va_end(parameters); |
2869 set_register(sp, entry_stack); | 3249 set_register(sp, entry_stack); |
2870 | 3250 |
2871 CallInternal(entry); | 3251 CallInternal(entry); |
2872 | 3252 |
2873 // Pop stack passed arguments. | 3253 // Pop stack passed arguments. |
2874 CHECK_EQ(entry_stack, get_register(sp)); | 3254 CHECK_EQ(entry_stack, get_register(sp)); |
2875 set_register(sp, original_stack); | 3255 set_register(sp, original_stack); |
2876 | 3256 |
2877 int32_t result = get_register(v0); | 3257 int64_t result = get_register(v0); |
2878 return result; | 3258 return result; |
2879 } | 3259 } |
2880 | 3260 |
2881 | 3261 |
2882 double Simulator::CallFP(byte* entry, double d0, double d1) { | 3262 double Simulator::CallFP(byte* entry, double d0, double d1) { |
2883 if (!IsMipsSoftFloatABI) { | 3263 if (!IsMipsSoftFloatABI) { |
| 3264 const FPURegister fparg2 = (kMipsAbi == kN64) ? f13 : f14; |
2884 set_fpu_register_double(f12, d0); | 3265 set_fpu_register_double(f12, d0); |
2885 set_fpu_register_double(f14, d1); | 3266 set_fpu_register_double(fparg2, d1); |
2886 } else { | 3267 } else { |
2887 int buffer[2]; | 3268 int buffer[2]; |
2888 ASSERT(sizeof(buffer[0]) * 2 == sizeof(d0)); | 3269 ASSERT(sizeof(buffer[0]) * 2 == sizeof(d0)); |
2889 memcpy(buffer, &d0, sizeof(d0)); | 3270 memcpy(buffer, &d0, sizeof(d0)); |
2890 set_dw_register(a0, buffer); | 3271 set_dw_register(a0, buffer); |
2891 memcpy(buffer, &d1, sizeof(d1)); | 3272 memcpy(buffer, &d1, sizeof(d1)); |
2892 set_dw_register(a2, buffer); | 3273 set_dw_register(a2, buffer); |
2893 } | 3274 } |
2894 CallInternal(entry); | 3275 CallInternal(entry); |
2895 if (!IsMipsSoftFloatABI) { | 3276 if (!IsMipsSoftFloatABI) { |
2896 return get_fpu_register_double(f0); | 3277 return get_fpu_register_double(f0); |
2897 } else { | 3278 } else { |
2898 return get_double_from_register_pair(v0); | 3279 return get_double_from_register_pair(v0); |
2899 } | 3280 } |
2900 } | 3281 } |
2901 | 3282 |
2902 | 3283 |
2903 uintptr_t Simulator::PushAddress(uintptr_t address) { | 3284 uintptr_t Simulator::PushAddress(uintptr_t address) { |
2904 int new_sp = get_register(sp) - sizeof(uintptr_t); | 3285 int64_t new_sp = get_register(sp) - sizeof(uintptr_t); |
2905 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(new_sp); | 3286 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(new_sp); |
2906 *stack_slot = address; | 3287 *stack_slot = address; |
2907 set_register(sp, new_sp); | 3288 set_register(sp, new_sp); |
2908 return new_sp; | 3289 return new_sp; |
2909 } | 3290 } |
2910 | 3291 |
2911 | 3292 |
2912 uintptr_t Simulator::PopAddress() { | 3293 uintptr_t Simulator::PopAddress() { |
2913 int current_sp = get_register(sp); | 3294 int64_t current_sp = get_register(sp); |
2914 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp); | 3295 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp); |
2915 uintptr_t address = *stack_slot; | 3296 uintptr_t address = *stack_slot; |
2916 set_register(sp, current_sp + sizeof(uintptr_t)); | 3297 set_register(sp, current_sp + sizeof(uintptr_t)); |
2917 return address; | 3298 return address; |
2918 } | 3299 } |
2919 | 3300 |
2920 | 3301 |
2921 #undef UNSUPPORTED | 3302 #undef UNSUPPORTED |
2922 | 3303 |
2923 } } // namespace v8::internal | 3304 } } // namespace v8::internal |
2924 | 3305 |
2925 #endif // USE_SIMULATOR | 3306 #endif // USE_SIMULATOR |
2926 | 3307 |
2927 #endif // V8_TARGET_ARCH_MIPS | 3308 #endif // V8_TARGET_ARCH_MIPS64 |
OLD | NEW |