Add mips64 port.

src/mips64/disasm-mips64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 12 matching lines @@
 // achieved by just calling Disassembler::Disassemble(stdout, begin, end);
 
 
 #include <assert.h>
 #include <stdarg.h>
 #include <stdio.h>
 #include <string.h>
 
 #include "src/v8.h"
 
-#if V8_TARGET_ARCH_MIPS
+#if V8_TARGET_ARCH_MIPS64
 
 #include "src/base/platform/platform.h"
 #include "src/disasm.h"
 #include "src/macro-assembler.h"
-#include "src/mips/constants-mips.h"
+#include "src/mips64/constants-mips64.h"
 
 namespace v8 {
 namespace internal {
 
 //------------------------------------------------------------------------------
 
 // Decoder decodes and disassembles instructions into an output buffer.
 // It uses the converter to convert register names and call destinations into
 // more informative description.
 class Decoder {
@@ skipping 41 matching lines @@
   void PrintCode(Instruction* instr);   // For break and trap instructions.
   // Printing of instruction name.
   void PrintInstructionName(Instruction* instr);
 
   // Handle formatting of instructions and their options.
   int FormatRegister(Instruction* instr, const char* option);
   int FormatFPURegister(Instruction* instr, const char* option);
   int FormatOption(Instruction* instr, const char* option);
   void Format(Instruction* instr, const char* format);
   void Unknown(Instruction* instr);
+  int DecodeBreakInstr(Instruction* instr);
 
   // Each of these functions decodes one particular instruction type.
-  void DecodeTypeRegister(Instruction* instr);
+  int DecodeTypeRegister(Instruction* instr);
   void DecodeTypeImmediate(Instruction* instr);
   void DecodeTypeJump(Instruction* instr);
 
   const disasm::NameConverter& converter_;
   v8::internal::Vector<char> out_buffer_;
   int out_buffer_pos_;
 
   DISALLOW_COPY_AND_ASSIGN(Decoder);
 };
 
@@ skipping 317 matching lines @@
 }
 
 
 // For currently unimplemented decodings the disassembler calls Unknown(instr)
 // which will just print "unknown" of the instruction bits.
 void Decoder::Unknown(Instruction* instr) {
   Format(instr, "unknown");
 }
 
 
-void Decoder::DecodeTypeRegister(Instruction* instr) {
+int Decoder::DecodeBreakInstr(Instruction* instr) {
+  // This is already known to be BREAK instr, just extract the code.
+  if (instr->Bits(25, 6) == static_cast<int>(kMaxStopCode)) {
+    // This is stop(msg).
+    Format(instr, "break, code: 'code");
+    out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                "\n%p       %08lx       stop msg: %s",
+                                static_cast<void*>
+                                      (reinterpret_cast<int32_t*>(instr
+                                              + Instruction::kInstrSize)),
+                                reinterpret_cast<uint64_t>
+                                (*reinterpret_cast<char**>(instr
+                                              + Instruction::kInstrSize)),
+                                *reinterpret_cast<char**>(instr
+                                              + Instruction::kInstrSize));
+    // Size 3: the break_ instr, plus embedded 64-bit char pointer.
+    return 3 * Instruction::kInstrSize;
+  } else {
+    Format(instr, "break, code: 'code");
+    return Instruction::kInstrSize;
+  }
+}
+
+
+int Decoder::DecodeTypeRegister(Instruction* instr) {
   switch (instr->OpcodeFieldRaw()) {
     case COP1:    // Coprocessor instructions.
       switch (instr->RsFieldRaw()) {
         case BC1:   // bc1 handled in DecodeTypeImmediate.
           UNREACHABLE();
           break;
         case MFC1:
           Format(instr, "mfc1    'rt, 'fs");
           break;
+        case DMFC1:
+          Format(instr, "dmfc1    'rt, 'fs");
+          break;
         case MFHC1:
           Format(instr, "mfhc1   'rt, 'fs");
           break;
         case MTC1:
           Format(instr, "mtc1    'rt, 'fs");
           break;
+        case DMTC1:
+          Format(instr, "dmtc1    'rt, 'fs");
+          break;
         // These are called "fs" too, although they are not FPU registers.
         case CTC1:
           Format(instr, "ctc1    'rt, 'fs");
           break;
         case CFC1:
           Format(instr, "cfc1    'rt, 'fs");
           break;
         case MTHC1:
           Format(instr, "mthc1   'rt, 'fs");
           break;
@@ skipping 19 matching lines @@
               break;
             case NEG_D:
               Format(instr, "neg.d   'fd, 'fs");
               break;
             case SQRT_D:
               Format(instr, "sqrt.d  'fd, 'fs");
               break;
             case CVT_W_D:
               Format(instr, "cvt.w.d 'fd, 'fs");
               break;
-            case CVT_L_D: {
-              if (kArchVariant == kMips32r2) {
-                Format(instr, "cvt.l.d 'fd, 'fs");
-              } else {
-                Unknown(instr);
-              }
+            case CVT_L_D:
+              Format(instr, "cvt.l.d 'fd, 'fs");
               break;
-            }
             case TRUNC_W_D:
               Format(instr, "trunc.w.d 'fd, 'fs");
               break;
-            case TRUNC_L_D: {
-              if (kArchVariant == kMips32r2) {
-                Format(instr, "trunc.l.d 'fd, 'fs");
-              } else {
-                Unknown(instr);
-              }
+            case TRUNC_L_D:
+              Format(instr, "trunc.l.d 'fd, 'fs");
               break;
-            }
             case ROUND_W_D:
               Format(instr, "round.w.d 'fd, 'fs");
               break;
+            case ROUND_L_D:
+              Format(instr, "round.l.d 'fd, 'fs");
+              break;
             case FLOOR_W_D:
               Format(instr, "floor.w.d 'fd, 'fs");
               break;
+            case FLOOR_L_D:
+              Format(instr, "floor.l.d 'fd, 'fs");
+              break;
             case CEIL_W_D:
               Format(instr, "ceil.w.d 'fd, 'fs");
               break;
+            case CEIL_L_D:
+              Format(instr, "ceil.l.d 'fd, 'fs");
+              break;
             case CVT_S_D:
               Format(instr, "cvt.s.d 'fd, 'fs");
               break;
             case C_F_D:
               Format(instr, "c.f.d   'fs, 'ft, 'Cc");
               break;
             case C_UN_D:
               Format(instr, "c.un.d  'fs, 'ft, 'Cc");
               break;
             case C_EQ_D:
@@ skipping 29 matching lines @@
               break;
             case CVT_D_W:   // Convert word to double.
               Format(instr, "cvt.d.w 'fd, 'fs");
               break;
             default:
               UNREACHABLE();
           }
           break;
         case L:
           switch (instr->FunctionFieldRaw()) {
-            case CVT_D_L: {
-              if (kArchVariant == kMips32r2) {
-                Format(instr, "cvt.d.l 'fd, 'fs");
-              } else {
-                Unknown(instr);
-              }
+            case CVT_D_L:
+              Format(instr, "cvt.d.l 'fd, 'fs");
               break;
-            }
-            case CVT_S_L: {
-              if (kArchVariant == kMips32r2) {
-                Format(instr, "cvt.s.l 'fd, 'fs");
-              } else {
-                Unknown(instr);
-              }
+            case CVT_S_L:
+              Format(instr, "cvt.s.l 'fd, 'fs");
               break;
-            }
             default:
               UNREACHABLE();
           }
           break;
         case PS:
           UNIMPLEMENTED_MIPS();
           break;
         default:
           UNREACHABLE();
       }
@@ skipping 14 matching lines @@
           break;
         case JALR:
           Format(instr, "jalr    'rs");
           break;
         case SLL:
           if ( 0x0 == static_cast<int>(instr->InstructionBits()))
             Format(instr, "nop");
           else
             Format(instr, "sll     'rd, 'rt, 'sa");
           break;
+        case DSLL:
+          Format(instr, "dsll    'rd, 'rt, 'sa");
+          break;
+        case DSLL32:
+          Format(instr, "dsll32  'rd, 'rt, 'sa");
+          break;
         case SRL:
           if (instr->RsValue() == 0) {
             Format(instr, "srl     'rd, 'rt, 'sa");
           } else {
-            if (kArchVariant == kMips32r2) {
+            if (kArchVariant == kMips64r2) {
               Format(instr, "rotr    'rd, 'rt, 'sa");
             } else {
               Unknown(instr);
             }
           }
           break;
+        case DSRL:
+          if (instr->RsValue() == 0) {
+            Format(instr, "dsrl    'rd, 'rt, 'sa");
+          } else {
+            if (kArchVariant == kMips64r2) {
+              Format(instr, "drotr   'rd, 'rt, 'sa");
+            } else {
+              Unknown(instr);
+            }
+          }
+          break;
+        case DSRL32:
+          Format(instr, "dsrl32  'rd, 'rt, 'sa");
+          break;
         case SRA:
           Format(instr, "sra     'rd, 'rt, 'sa");
           break;
+        case DSRA:
+          Format(instr, "dsra    'rd, 'rt, 'sa");
+          break;
+        case DSRA32:
+          Format(instr, "dsra32  'rd, 'rt, 'sa");
+          break;
         case SLLV:
           Format(instr, "sllv    'rd, 'rt, 'rs");
           break;
+        case DSLLV:
+          Format(instr, "dsllv   'rd, 'rt, 'rs");
+          break;
         case SRLV:
           if (instr->SaValue() == 0) {
             Format(instr, "srlv    'rd, 'rt, 'rs");
           } else {
-            if (kArchVariant == kMips32r2) {
+            if (kArchVariant == kMips64r2) {
               Format(instr, "rotrv   'rd, 'rt, 'rs");
             } else {
               Unknown(instr);
             }
           }
           break;
+        case DSRLV:
+          if (instr->SaValue() == 0) {
+            Format(instr, "dsrlv   'rd, 'rt, 'rs");
+          } else {
+            if (kArchVariant == kMips64r2) {
+              Format(instr, "drotrv  'rd, 'rt, 'rs");
+            } else {
+              Unknown(instr);
+            }
+          }
+          break;
         case SRAV:
           Format(instr, "srav    'rd, 'rt, 'rs");
           break;
+        case DSRAV:
+          Format(instr, "dsrav   'rd, 'rt, 'rs");
+          break;
         case MFHI:
           Format(instr, "mfhi    'rd");
           break;
         case MFLO:
           Format(instr, "mflo    'rd");
           break;
         case MULT:
           Format(instr, "mult    'rs, 'rt");
           break;
+        case DMULT:
+          Format(instr, "dmult   'rs, 'rt");
+          break;
         case MULTU:
           Format(instr, "multu   'rs, 'rt");
           break;
+        case DMULTU:
+          Format(instr, "dmultu  'rs, 'rt");
+          break;
         case DIV:
           Format(instr, "div     'rs, 'rt");
           break;
+        case DDIV:
+          Format(instr, "ddiv    'rs, 'rt");
+          break;
         case DIVU:
           Format(instr, "divu    'rs, 'rt");
           break;
+        case DDIVU:
+          Format(instr, "ddivu   'rs, 'rt");
+          break;
         case ADD:
           Format(instr, "add     'rd, 'rs, 'rt");
           break;
+        case DADD:
+          Format(instr, "dadd    'rd, 'rs, 'rt");
+          break;
         case ADDU:
           Format(instr, "addu    'rd, 'rs, 'rt");
           break;
+        case DADDU:
+          Format(instr, "daddu   'rd, 'rs, 'rt");
+          break;
         case SUB:
           Format(instr, "sub     'rd, 'rs, 'rt");
           break;
+        case DSUB:
+          Format(instr, "dsub    'rd, 'rs, 'rt");
+          break;
         case SUBU:
           Format(instr, "subu    'rd, 'rs, 'rt");
           break;
+        case DSUBU:
+          Format(instr, "dsubu   'rd, 'rs, 'rt");
+          break;
         case AND:
           Format(instr, "and     'rd, 'rs, 'rt");
           break;
         case OR:
           if (0 == instr->RsValue()) {
             Format(instr, "mov     'rd, 'rt");
           } else if (0 == instr->RtValue()) {
             Format(instr, "mov     'rd, 'rs");
           } else {
             Format(instr, "or      'rd, 'rs, 'rt");
           }
           break;
         case XOR:
           Format(instr, "xor     'rd, 'rs, 'rt");
           break;
         case NOR:
           Format(instr, "nor     'rd, 'rs, 'rt");
           break;
         case SLT:
           Format(instr, "slt     'rd, 'rs, 'rt");
           break;
         case SLTU:
           Format(instr, "sltu    'rd, 'rs, 'rt");
           break;
         case BREAK:
-          Format(instr, "break, code: 'code");
-          break;
+          return DecodeBreakInstr(instr);
         case TGE:
           Format(instr, "tge     'rs, 'rt, code: 'code");
           break;
         case TGEU:
           Format(instr, "tgeu    'rs, 'rt, code: 'code");
           break;
         case TLT:
           Format(instr, "tlt     'rs, 'rt, code: 'code");
           break;
         case TLTU:
@@ skipping 30 matching lines @@
         case CLZ:
           Format(instr, "clz     'rd, 'rs");
           break;
         default:
           UNREACHABLE();
       }
       break;
     case SPECIAL3:
       switch (instr->FunctionFieldRaw()) {
         case INS: {
-          if (kArchVariant == kMips32r2) {
+          if (kArchVariant == kMips64r2) {
             Format(instr, "ins     'rt, 'rs, 'sa, 'ss2");
           } else {
             Unknown(instr);
           }
           break;
         }
         case EXT: {
-          if (kArchVariant == kMips32r2) {
+          if (kArchVariant == kMips64r2) {
             Format(instr, "ext     'rt, 'rs, 'sa, 'ss1");
           } else {
             Unknown(instr);
           }
           break;
         }
         default:
           UNREACHABLE();
       }
       break;
     default:
       UNREACHABLE();
   }
+  return Instruction::kInstrSize;
 }
 
 
 void Decoder::DecodeTypeImmediate(Instruction* instr) {
   switch (instr->OpcodeFieldRaw()) {
     // ------------- REGIMM class.
     case COP1:
       switch (instr->RsFieldRaw()) {
         case BC1:
           if (instr->FBtrueValue()) {
@@ skipping 34 matching lines @@
     case BLEZ:
       Format(instr, "blez    'rs, 'imm16u");
       break;
     case BGTZ:
       Format(instr, "bgtz    'rs, 'imm16u");
       break;
     // ------------- Arithmetic instructions.
     case ADDI:
       Format(instr, "addi    'rt, 'rs, 'imm16s");
       break;
+    case DADDI:
+      Format(instr, "daddi   'rt, 'rs, 'imm16s");
+      break;
     case ADDIU:
       Format(instr, "addiu   'rt, 'rs, 'imm16s");
       break;
+    case DADDIU:
+      Format(instr, "daddiu  'rt, 'rs, 'imm16s");
+      break;
     case SLTI:
       Format(instr, "slti    'rt, 'rs, 'imm16s");
       break;
     case SLTIU:
       Format(instr, "sltiu   'rt, 'rs, 'imm16u");
       break;
     case ANDI:
       Format(instr, "andi    'rt, 'rs, 'imm16x");
       break;
     case ORI:
       Format(instr, "ori     'rt, 'rs, 'imm16x");
       break;
     case XORI:
       Format(instr, "xori    'rt, 'rs, 'imm16x");
       break;
     case LUI:
       Format(instr, "lui     'rt, 'imm16x");
       break;
     // ------------- Memory instructions.
     case LB:
       Format(instr, "lb      'rt, 'imm16s('rs)");
       break;
     case LH:
       Format(instr, "lh      'rt, 'imm16s('rs)");
       break;
     case LWL:
       Format(instr, "lwl     'rt, 'imm16s('rs)");
       break;
+    case LDL:
+      Format(instr, "ldl     'rt, 'imm16s('rs)");
+      break;
     case LW:
       Format(instr, "lw      'rt, 'imm16s('rs)");
       break;
+    case LWU:
+      Format(instr, "lwu     'rt, 'imm16s('rs)");
+      break;
+    case LD:
+      Format(instr, "ld      'rt, 'imm16s('rs)");
+      break;
     case LBU:
       Format(instr, "lbu     'rt, 'imm16s('rs)");
       break;
     case LHU:
       Format(instr, "lhu     'rt, 'imm16s('rs)");
       break;
     case LWR:
       Format(instr, "lwr     'rt, 'imm16s('rs)");
       break;
+    case LDR:
+      Format(instr, "ldr     'rt, 'imm16s('rs)");
+      break;
     case PREF:
       Format(instr, "pref    'rt, 'imm16s('rs)");
       break;
     case SB:
       Format(instr, "sb      'rt, 'imm16s('rs)");
       break;
     case SH:
       Format(instr, "sh      'rt, 'imm16s('rs)");
       break;
     case SWL:
       Format(instr, "swl     'rt, 'imm16s('rs)");
       break;
     case SW:
       Format(instr, "sw      'rt, 'imm16s('rs)");
       break;
+    case SD:
+      Format(instr, "sd      'rt, 'imm16s('rs)");
+      break;
     case SWR:
       Format(instr, "swr     'rt, 'imm16s('rs)");
       break;
     case LWC1:
       Format(instr, "lwc1    'ft, 'imm16s('rs)");
       break;
     case LDC1:
       Format(instr, "ldc1    'ft, 'imm16s('rs)");
       break;
     case SWC1:
       Format(instr, "swc1    'ft, 'imm16s('rs)");
       break;
     case SDC1:
       Format(instr, "sdc1    'ft, 'imm16s('rs)");
       break;
     default:
-      UNREACHABLE();
+      printf("a 0x%x \n", instr->OpcodeFieldRaw());
+    UNREACHABLE();
       break;
   }
 }
 
 
 void Decoder::DecodeTypeJump(Instruction* instr) {
   switch (instr->OpcodeFieldRaw()) {
     case J:
       Format(instr, "j       'imm26x");
       break;
     case JAL:
       Format(instr, "jal     'imm26x");
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 // Disassemble the instruction at *instr_ptr into the output buffer.
+// All instructions are one word long, except for the simulator
+// psuedo-instruction stop(msg). For that one special case, we return
+// size larger than one kInstrSize.
 int Decoder::InstructionDecode(byte* instr_ptr) {
   Instruction* instr = Instruction::At(instr_ptr);
   // Print raw instruction bytes.
   out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                   "%08x       ",
-                                   instr->InstructionBits());
+                              "%08x       ",
+                              instr->InstructionBits());
   switch (instr->InstructionType()) {
     case Instruction::kRegisterType: {
-      DecodeTypeRegister(instr);
-      break;
+      return DecodeTypeRegister(instr);
     }
     case Instruction::kImmediateType: {
       DecodeTypeImmediate(instr);
       break;
     }
     case Instruction::kJumpType: {
       DecodeTypeJump(instr);
       break;
     }
     default: {
@@ skipping 80 matching lines @@
     v8::internal::PrintF(f, "%p    %08x      %s\n",
         prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 #undef UNSUPPORTED
 
 }  // namespace disasm
 
-#endif  // V8_TARGET_ARCH_MIPS
+#endif  // V8_TARGET_ARCH_MIPS64