Add mips64 port.

src/mips64/constants-mips64.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef  V8_MIPS_CONSTANTS_H_
 #define  V8_MIPS_CONSTANTS_H_
 
 // UNIMPLEMENTED_ macro for MIPS.
 #ifdef DEBUG
 #define UNIMPLEMENTED_MIPS()                                                  \
   v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n",    \
                        __FILE__, __LINE__, __func__)
 #else
 #define UNIMPLEMENTED_MIPS()
 #endif
 
 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n")
 
 enum ArchVariants {
   kMips32r2,
   kMips32r1,
-  kLoongson
+  kLoongson,
+  kMips64r2
 };
 
-#ifdef _MIPS_ARCH_MIPS32R2
-  static const ArchVariants kArchVariant = kMips32r2;
+
+#ifdef _MIPS_ARCH_MIPS64R2
+  static const ArchVariants kArchVariant = kMips64r2;
 #elif _MIPS_ARCH_LOONGSON
 // The loongson flag refers to the LOONGSON architectures based on MIPS-III,
 // which predates (and is a subset of) the mips32r2 and r1 architectures.
   static const ArchVariants kArchVariant = kLoongson;
 #else
-  static const ArchVariants kArchVariant = kMips32r1;
+  static const ArchVariants kArchVariant = kMips64r1;
 #endif
 
-enum Endianness {
-  kLittle,
-  kBig
+
+// TODO(plind): consider deriving ABI from compiler flags or build system.
+
+// ABI-dependent definitions are made with #define in simulator-mips64.h,
+// so the ABI choice must be available to the pre-processor. However, in all
+// other cases, we should use the enum AbiVariants with normal if statements.
+
+#define MIPS_ABI_N64 1
+// #define MIPS_ABI_O32 1
+
+// The only supported Abi's are O32, and n64.
+enum AbiVariants {
+  kO32,
+  kN64  // Use upper case N for 'n64' ABI to conform to style standard.
 };
 
-#if defined(V8_TARGET_LITTLE_ENDIAN)
-  static const Endianness kArchEndian = kLittle;
-#elif defined(V8_TARGET_BIG_ENDIAN)
-  static const Endianness kArchEndian = kBig;
+#ifdef MIPS_ABI_N64
+static const AbiVariants kMipsAbi = kN64;
 #else
-#error Unknown endianness
+static const AbiVariants kMipsAbi = kO32;
 #endif
 
+
+// TODO(plind): consider renaming these ...
 #if(defined(__mips_hard_float) && __mips_hard_float != 0)
 // Use floating-point coprocessor instructions. This flag is raised when
 // -mhard-float is passed to the compiler.
 const bool IsMipsSoftFloatABI = false;
 #elif(defined(__mips_soft_float) && __mips_soft_float != 0)
 // This flag is raised when -msoft-float is passed to the compiler.
 // Although FPU is a base requirement for v8, soft-float ABI is used
 // on soft-float systems with FPU kernel emulation.
 const bool IsMipsSoftFloatABI = true;
 #else
 const bool IsMipsSoftFloatABI = true;
 #endif
 
-#if defined(V8_TARGET_LITTLE_ENDIAN)
-const uint32_t kHoleNanUpper32Offset = 4;
-const uint32_t kHoleNanLower32Offset = 0;
-#elif defined(V8_TARGET_BIG_ENDIAN)
-const uint32_t kHoleNanUpper32Offset = 0;
-const uint32_t kHoleNanLower32Offset = 4;
-#else
-#error Unknown endianness
-#endif
+
+#define __STDC_FORMAT_MACROS
+#include <inttypes.h>
+
 
 // Defines constants and accessor classes to assemble, disassemble and
 // simulate MIPS32 instructions.
 //
 // See: MIPS32 Architecture For Programmers
 //      Volume II: The MIPS32 Instruction Set
 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf.
 
 namespace v8 {
 namespace internal {
@@ skipping 12 matching lines @@
 const int kPCRegister = 34;
 
 // Number coprocessor registers.
 const int kNumFPURegisters = 32;
 const int kInvalidFPURegister = -1;
 
 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
 const int kFCSRRegister = 31;
 const int kInvalidFPUControlRegister = -1;
 const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1;
+const uint64_t kFPU64InvalidResult =
+    static_cast<uint64_t>(static_cast<uint64_t>(1) << 63) - 1;
 
 // FCSR constants.
 const uint32_t kFCSRInexactFlagBit = 2;
 const uint32_t kFCSRUnderflowFlagBit = 3;
 const uint32_t kFCSROverflowFlagBit = 4;
 const uint32_t kFCSRDivideByZeroFlagBit = 5;
 const uint32_t kFCSRInvalidOpFlagBit = 6;
 
 const uint32_t kFCSRInexactFlagMask = 1 << kFCSRInexactFlagBit;
 const uint32_t kFCSRUnderflowFlagMask = 1 << kFCSRUnderflowFlagBit;
@@ skipping 27 matching lines @@
   static const char* Name(int reg);
 
   // Lookup the register number for the name provided.
   static int Number(const char* name);
 
   struct RegisterAlias {
     int reg;
     const char* name;
   };
 
-  static const int32_t kMaxValue = 0x7fffffff;
-  static const int32_t kMinValue = 0x80000000;
+  static const int64_t kMaxValue = 0x7fffffffffffffffl;
+  static const int64_t kMinValue = 0x8000000000000000l;
 
  private:
   static const char* names_[kNumSimuRegisters];
   static const RegisterAlias aliases_[];
 };
 
 // Helper functions for converting between register numbers and names.
 class FPURegisters {
  public:
   // Return the name of the register.
@@ skipping 52 matching lines @@
 const int kFunctionShift = 0;
 const int kFunctionBits  = 6;
 const int kLuiShift      = 16;
 
 const int kImm16Shift = 0;
 const int kImm16Bits  = 16;
 const int kImm26Shift = 0;
 const int kImm26Bits  = 26;
 const int kImm28Shift = 0;
 const int kImm28Bits  = 28;
+const int kImm32Shift = 0;
+const int kImm32Bits  = 32;
 
 // In branches and jumps immediate fields point to words, not bytes,
 // and are therefore shifted by 2.
 const int kImmFieldShift = 2;
 
 const int kFrBits        = 5;
 const int kFrShift       = 21;
 const int kFsShift       = 11;
 const int kFsBits        = 5;
 const int kFtShift       = 16;
@@ skipping 16 matching lines @@
 const int  kRsFieldMask  = ((1 << kRsBits) - 1) << kRsShift;
 const int  kRtFieldMask  = ((1 << kRtBits) - 1) << kRtShift;
 const int  kRdFieldMask  = ((1 << kRdBits) - 1) << kRdShift;
 const int  kSaFieldMask  = ((1 << kSaBits) - 1) << kSaShift;
 const int  kFunctionFieldMask = ((1 << kFunctionBits) - 1) << kFunctionShift;
 // Misc masks.
 const int  kHiMask       =   0xffff << 16;
 const int  kLoMask       =   0xffff;
 const int  kSignMask     =   0x80000000;
 const int  kJumpAddrMask = (1 << (kImm26Bits + kImmFieldShift)) - 1;
+const int64_t  kHi16MaskOf64 =   (int64_t)0xffff << 48;
+const int64_t  kSe16MaskOf64 =   (int64_t)0xffff << 32;
+const int64_t  kTh16MaskOf64 =   (int64_t)0xffff << 16;
 
 // ----- MIPS Opcodes and Function Fields.
 // We use this presentation to stay close to the table representation in
 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set.
 enum Opcode {
   SPECIAL   =   0 << kOpcodeShift,
   REGIMM    =   1 << kOpcodeShift,
 
   J         =   ((0 << 3) + 2) << kOpcodeShift,
   JAL       =   ((0 << 3) + 3) << kOpcodeShift,
@@ skipping 10 matching lines @@
   ORI       =   ((1 << 3) + 5) << kOpcodeShift,
   XORI      =   ((1 << 3) + 6) << kOpcodeShift,
   LUI       =   ((1 << 3) + 7) << kOpcodeShift,
 
   COP1      =   ((2 << 3) + 1) << kOpcodeShift,  // Coprocessor 1 class.
   BEQL      =   ((2 << 3) + 4) << kOpcodeShift,
   BNEL      =   ((2 << 3) + 5) << kOpcodeShift,
   BLEZL     =   ((2 << 3) + 6) << kOpcodeShift,
   BGTZL     =   ((2 << 3) + 7) << kOpcodeShift,
 
+  DADDI     =   ((3 << 3) + 0) << kOpcodeShift,
+  DADDIU    =   ((3 << 3) + 1) << kOpcodeShift,
+  LDL       =   ((3 << 3) + 2) << kOpcodeShift,
+  LDR       =   ((3 << 3) + 3) << kOpcodeShift,
   SPECIAL2  =   ((3 << 3) + 4) << kOpcodeShift,
   SPECIAL3  =   ((3 << 3) + 7) << kOpcodeShift,
 
   LB        =   ((4 << 3) + 0) << kOpcodeShift,
   LH        =   ((4 << 3) + 1) << kOpcodeShift,
   LWL       =   ((4 << 3) + 2) << kOpcodeShift,
   LW        =   ((4 << 3) + 3) << kOpcodeShift,
   LBU       =   ((4 << 3) + 4) << kOpcodeShift,
   LHU       =   ((4 << 3) + 5) << kOpcodeShift,
   LWR       =   ((4 << 3) + 6) << kOpcodeShift,
+  LWU       =   ((4 << 3) + 7) << kOpcodeShift,
+
   SB        =   ((5 << 3) + 0) << kOpcodeShift,
   SH        =   ((5 << 3) + 1) << kOpcodeShift,
   SWL       =   ((5 << 3) + 2) << kOpcodeShift,
   SW        =   ((5 << 3) + 3) << kOpcodeShift,
+  SDL       =   ((5 << 3) + 4) << kOpcodeShift,
+  SDR       =   ((5 << 3) + 5) << kOpcodeShift,
   SWR       =   ((5 << 3) + 6) << kOpcodeShift,
 
   LWC1      =   ((6 << 3) + 1) << kOpcodeShift,
+  LLD       =   ((6 << 3) + 4) << kOpcodeShift,
   LDC1      =   ((6 << 3) + 5) << kOpcodeShift,
+  LD        =   ((6 << 3) + 7) << kOpcodeShift,
 
   PREF      =   ((6 << 3) + 3) << kOpcodeShift,
 
   SWC1      =   ((7 << 3) + 1) << kOpcodeShift,
+  SCD       =   ((7 << 3) + 4) << kOpcodeShift,
   SDC1      =   ((7 << 3) + 5) << kOpcodeShift,
+  SD        =   ((7 << 3) + 7) << kOpcodeShift,
 
   COP1X     =   ((1 << 4) + 3) << kOpcodeShift
 };
 
 enum SecondaryField {
   // SPECIAL Encoding of Function Field.
   SLL       =   ((0 << 3) + 0),
   MOVCI     =   ((0 << 3) + 1),
   SRL       =   ((0 << 3) + 2),
   SRA       =   ((0 << 3) + 3),
   SLLV      =   ((0 << 3) + 4),
   SRLV      =   ((0 << 3) + 6),
   SRAV      =   ((0 << 3) + 7),
 
   JR        =   ((1 << 3) + 0),
   JALR      =   ((1 << 3) + 1),
   MOVZ      =   ((1 << 3) + 2),
   MOVN      =   ((1 << 3) + 3),
   BREAK     =   ((1 << 3) + 5),
 
   MFHI      =   ((2 << 3) + 0),
   MFLO      =   ((2 << 3) + 2),
+  DSLLV     =   ((2 << 3) + 4),
+  DSRLV     =   ((2 << 3) + 6),
+  DSRAV     =   ((2 << 3) + 7),
 
   MULT      =   ((3 << 3) + 0),
   MULTU     =   ((3 << 3) + 1),
   DIV       =   ((3 << 3) + 2),
   DIVU      =   ((3 << 3) + 3),
+  DMULT     =   ((3 << 3) + 4),
+  DMULTU    =   ((3 << 3) + 5),
+  DDIV      =   ((3 << 3) + 6),
+  DDIVU     =   ((3 << 3) + 7),
 
   ADD       =   ((4 << 3) + 0),
   ADDU      =   ((4 << 3) + 1),
   SUB       =   ((4 << 3) + 2),
   SUBU      =   ((4 << 3) + 3),
   AND       =   ((4 << 3) + 4),
   OR        =   ((4 << 3) + 5),
   XOR       =   ((4 << 3) + 6),
   NOR       =   ((4 << 3) + 7),
 
   SLT       =   ((5 << 3) + 2),
   SLTU      =   ((5 << 3) + 3),
+  DADD      =   ((5 << 3) + 4),
+  DADDU     =   ((5 << 3) + 5),
+  DSUB      =   ((5 << 3) + 6),
+  DSUBU     =   ((5 << 3) + 7),
 
   TGE       =   ((6 << 3) + 0),
   TGEU      =   ((6 << 3) + 1),
   TLT       =   ((6 << 3) + 2),
   TLTU      =   ((6 << 3) + 3),
   TEQ       =   ((6 << 3) + 4),
   TNE       =   ((6 << 3) + 6),
 
+  DSLL      =   ((7 << 3) + 0),
+  DSRL      =   ((7 << 3) + 2),
+  DSRA      =   ((7 << 3) + 3),
+  DSLL32    =   ((7 << 3) + 4),
+  DSRL32    =   ((7 << 3) + 6),
+  DSRA32    =   ((7 << 3) + 7),
+  // drotr in special4?
+
   // SPECIAL2 Encoding of Function Field.
   MUL       =   ((0 << 3) + 2),
   CLZ       =   ((4 << 3) + 0),
   CLO       =   ((4 << 3) + 1),
 
   // SPECIAL3 Encoding of Function Field.
   EXT       =   ((0 << 3) + 0),
+  DEXTM     =   ((0 << 3) + 1),
+  DEXTU     =   ((0 << 3) + 2),
+  DEXT      =   ((0 << 3) + 3),
   INS       =   ((0 << 3) + 4),
+  DINSM     =   ((0 << 3) + 5),
+  DINSU     =   ((0 << 3) + 6),
+  DINS      =   ((0 << 3) + 7),
+
+  DSBH      =   ((4 << 3) + 4),
 
   // REGIMM  encoding of rt Field.
   BLTZ      =   ((0 << 3) + 0) << 16,
   BGEZ      =   ((0 << 3) + 1) << 16,
   BLTZAL    =   ((2 << 3) + 0) << 16,
   BGEZAL    =   ((2 << 3) + 1) << 16,
 
   // COP1 Encoding of rs Field.
   MFC1      =   ((0 << 3) + 0) << 21,
+  DMFC1     =   ((0 << 3) + 1) << 21,
   CFC1      =   ((0 << 3) + 2) << 21,
   MFHC1     =   ((0 << 3) + 3) << 21,
   MTC1      =   ((0 << 3) + 4) << 21,
+  DMTC1     =   ((0 << 3) + 5) << 21,
   CTC1      =   ((0 << 3) + 6) << 21,
   MTHC1     =   ((0 << 3) + 7) << 21,
   BC1       =   ((1 << 3) + 0) << 21,
   S         =   ((2 << 3) + 0) << 21,
   D         =   ((2 << 3) + 1) << 21,
   W         =   ((2 << 3) + 4) << 21,
   L         =   ((2 << 3) + 5) << 21,
   PS        =   ((2 << 3) + 6) << 21,
   // COP1 Encoding of Function Field When rs=S.
   ROUND_L_S =   ((1 << 3) + 0),
@@ skipping 409 matching lines @@
  private:
   // We need to prevent the creation of instances of class Instruction.
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
 };
 
 
 // -----------------------------------------------------------------------------
 // MIPS assembly various constants.
 
 // C/C++ argument slots size.
-const int kCArgSlotCount = 4;
-const int kCArgsSlotsSize = kCArgSlotCount * Instruction::kInstrSize;
-// JS argument slots size.
-const int kJSArgsSlotsSize = 0 * Instruction::kInstrSize;
-// Assembly builtins argument slots size.
-const int kBArgsSlotsSize = 0 * Instruction::kInstrSize;
+const int kCArgSlotCount = (kMipsAbi == kN64) ? 0 : 4;
+
+// TODO(plind): below should be based on kPointerSize
+// TODO(plind): find all usages and remove the needless instructions for n64.
+const int kCArgsSlotsSize = kCArgSlotCount * Instruction::kInstrSize * 2;
 
 const int kBranchReturnOffset = 2 * Instruction::kInstrSize;
 
 } }   // namespace v8::internal
 
 #endif    // #ifndef V8_MIPS_CONSTANTS_H_