| OLD | NEW |
| 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// | 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // This file implements the TargetLoweringX8632 class, which | 10 // This file implements the TargetLoweringX8632 class, which |
| (...skipping 2551 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 2562 Reg->setWeightInfinite(); | 2562 Reg->setWeightInfinite(); |
| 2563 else | 2563 else |
| 2564 Reg->setRegNum(RegNum); | 2564 Reg->setRegNum(RegNum); |
| 2565 return Reg; | 2565 return Reg; |
| 2566 } | 2566 } |
| 2567 | 2567 |
| 2568 void TargetX8632::postLower() { | 2568 void TargetX8632::postLower() { |
| 2569 if (Ctx->getOptLevel() != Opt_m1) | 2569 if (Ctx->getOptLevel() != Opt_m1) |
| 2570 return; | 2570 return; |
| 2571 // TODO: Avoid recomputing WhiteList every instruction. | 2571 // TODO: Avoid recomputing WhiteList every instruction. |
| 2572 llvm::SmallBitVector WhiteList = getRegisterSet(RegSet_All, RegSet_None); | 2572 RegSetMask RegInclude = RegSet_All; |
| 2573 RegSetMask RegExclude = RegSet_None; |
| 2574 if (hasFramePointer()) |
| 2575 RegExclude |= RegSet_FramePointer; |
| 2576 llvm::SmallBitVector WhiteList = getRegisterSet(RegInclude, RegExclude); |
| 2573 // Make one pass to black-list pre-colored registers. TODO: If | 2577 // Make one pass to black-list pre-colored registers. TODO: If |
| 2574 // there was some prior register allocation pass that made register | 2578 // there was some prior register allocation pass that made register |
| 2575 // assignments, those registers need to be black-listed here as | 2579 // assignments, those registers need to be black-listed here as |
| 2576 // well. | 2580 // well. |
| 2577 for (InstList::iterator I = Context.getCur(), E = Context.getEnd(); I != E; | 2581 for (InstList::iterator I = Context.getCur(), E = Context.getEnd(); I != E; |
| 2578 ++I) { | 2582 ++I) { |
| 2579 const Inst *Inst = *I; | 2583 const Inst *Inst = *I; |
| 2580 if (Inst->isDeleted()) | 2584 if (Inst->isDeleted()) |
| 2581 continue; | 2585 continue; |
| 2582 if (llvm::isa<InstFakeKill>(Inst)) | 2586 if (llvm::isa<InstFakeKill>(Inst)) |
| (...skipping 151 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 2734 for (SizeT i = 0; i < Size; ++i) { | 2738 for (SizeT i = 0; i < Size; ++i) { |
| 2735 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n"; | 2739 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n"; |
| 2736 } | 2740 } |
| 2737 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; | 2741 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; |
| 2738 } | 2742 } |
| 2739 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName | 2743 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName |
| 2740 << "\n"; | 2744 << "\n"; |
| 2741 } | 2745 } |
| 2742 | 2746 |
| 2743 } // end of namespace Ice | 2747 } // end of namespace Ice |
| OLD | NEW |