Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(870)

Issues Search
    My Issues | Starred     Open | Closed | All

Side by Side Diff: src/IceInstX8632.def

Issue 369573005: Avoid assigning esp (or ebp for framepointer-using frames) in Om1. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: add comment Created 6 years, 5 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « no previous file | src/IceTargetLowering.cpp » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-32 instructions in the 10 // This file defines properties of lowered x86-32 instructions in the
11 // form of x-macros. 11 // form of x-macros.
12 // 12 //
13 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===//
14 14
15 #ifndef SUBZERO_SRC_ICEINSTX8632_DEF 15 #ifndef SUBZERO_SRC_ICEINSTX8632_DEF
16 #define SUBZERO_SRC_ICEINSTX8632_DEF 16 #define SUBZERO_SRC_ICEINSTX8632_DEF
17 17
18 // NOTE: esp is not considered isInt, to avoid register allocating it.
18 #define REGX8632_TABLE \ 19 #define REGX8632_TABLE \
19 /* val, init, name, name16, name8, scratch, preserved, stackptr, \ 20 /* val, init, name, name16, name8, scratch, preserved, stackptr, \
20 frameptr, isI8, isInt, isFP */ \ 21 frameptr, isI8, isInt, isFP */ \
21 X(Reg_eax, = 0, "eax", "ax", "al", 1, 0, 0, 0, 1, 1, 0) \ 22 X(Reg_eax, = 0, "eax", "ax", "al", 1, 0, 0, 0, 1, 1, 0) \
22 X(Reg_ecx, = Reg_eax + 1, "ecx", "cx", "cl", 1, 0, 0, 0, 1, 1, 0) \ 23 X(Reg_ecx, = Reg_eax + 1, "ecx", "cx", "cl", 1, 0, 0, 0, 1, 1, 0) \
23 X(Reg_edx, = Reg_eax + 2, "edx", "dx", "dl", 1, 0, 0, 0, 1, 1, 0) \ 24 X(Reg_edx, = Reg_eax + 2, "edx", "dx", "dl", 1, 0, 0, 0, 1, 1, 0) \
24 X(Reg_ebx, = Reg_eax + 3, "ebx", "bx", "bl", 0, 1, 0, 0, 1, 1, 0) \ 25 X(Reg_ebx, = Reg_eax + 3, "ebx", "bx", "bl", 0, 1, 0, 0, 1, 1, 0) \
25 X(Reg_esp, = Reg_eax + 4, "esp", "sp", "" , 0, 0, 1, 0, 0, 1, 0) \ 26 X(Reg_esp, = Reg_eax + 4, "esp", "sp", "" , 0, 0, 1, 0, 0, 0, 0) \
26 X(Reg_ebp, = Reg_eax + 5, "ebp", "bp", "" , 0, 1, 0, 1, 0, 1, 0) \ 27 X(Reg_ebp, = Reg_eax + 5, "ebp", "bp", "" , 0, 1, 0, 1, 0, 1, 0) \
27 X(Reg_esi, = Reg_eax + 6, "esi", "si", "" , 0, 1, 0, 0, 0, 1, 0) \ 28 X(Reg_esi, = Reg_eax + 6, "esi", "si", "" , 0, 1, 0, 0, 0, 1, 0) \
28 X(Reg_edi, = Reg_eax + 7, "edi", "di", "" , 0, 1, 0, 0, 0, 1, 0) \ 29 X(Reg_edi, = Reg_eax + 7, "edi", "di", "" , 0, 1, 0, 0, 0, 1, 0) \
29 X(Reg_ah, = Reg_edi + 1, "???", "" , "ah", 0, 0, 0, 0, 1, 0, 0) \ 30 X(Reg_ah, = Reg_edi + 1, "???", "" , "ah", 0, 0, 0, 0, 1, 0, 0) \
30 X(Reg_xmm0, = Reg_ah + 1, "xmm0", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 31 X(Reg_xmm0, = Reg_ah + 1, "xmm0", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
31 X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 32 X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
32 X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 33 X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
33 X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 34 X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
34 X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 35 X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
35 X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 36 X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
(...skipping 42 matching lines...) Expand 10 before | Expand all | Expand 10 after
78 X(IceType_v4i1, "?", "" , "xmmword ptr") \ 79 X(IceType_v4i1, "?", "" , "xmmword ptr") \
79 X(IceType_v8i1, "?", "" , "xmmword ptr") \ 80 X(IceType_v8i1, "?", "" , "xmmword ptr") \
80 X(IceType_v16i1, "?", "" , "xmmword ptr") \ 81 X(IceType_v16i1, "?", "" , "xmmword ptr") \
81 X(IceType_v16i8, "?", "" , "xmmword ptr") \ 82 X(IceType_v16i8, "?", "" , "xmmword ptr") \
82 X(IceType_v8i16, "?", "" , "xmmword ptr") \ 83 X(IceType_v8i16, "?", "" , "xmmword ptr") \
83 X(IceType_v4i32, "?", "" , "xmmword ptr") \ 84 X(IceType_v4i32, "?", "" , "xmmword ptr") \
84 X(IceType_v4f32, "?", "" , "xmmword ptr") \ 85 X(IceType_v4f32, "?", "" , "xmmword ptr") \
85 //#define X(tag, cvt, sdss, width) 86 //#define X(tag, cvt, sdss, width)
86 87
87 #endif // SUBZERO_SRC_ICEINSTX8632_DEF 88 #endif // SUBZERO_SRC_ICEINSTX8632_DEF
OLDNEW
« no previous file with comments | « no previous file | src/IceTargetLowering.cpp » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698