ARM64: Generate better immediates for shifted ops

ARM64: Generate better immediates for shifted ops

Improve code generated for immediate data processing operations where the shift
on the operation can be exploited to use fewer instructions for the immediate.

For example, Add(x0, x0, 0x1f7de) used to generate:
  movz x16, 0xf7de
  movk x16, 0x1, lsl #16
  add x0, x0, x16

now generates:
  movz x16, 0xfbef
  add x0, x0, x16, lsl #1

BUG=
R=ulan@chromium.org

Committed: https://code.google.com/p/v8/source/detail?r=22246

[ulan, 2014-07-07 07:42:20]

lgtm

https://codereview.chromium.org/368313002/diff/1/src/arm64/macro-assembler-ar...
File src/arm64/macro-assembler-arm64.cc (right):

https://codereview.chromium.org/368313002/diff/1/src/arm64/macro-assembler-ar...
src/arm64/macro-assembler-arm64.cc:449: // inserting set bits in the
least-significant bits.
Could you please add a comment explaining why we fill with set bits instead of
zeros?

[m.m.capewell, 2014-07-07 13:28:03]

https://codereview.chromium.org/368313002/diff/1/src/arm64/macro-assembler-ar...
File src/arm64/macro-assembler-arm64.cc (right):

https://codereview.chromium.org/368313002/diff/1/src/arm64/macro-assembler-ar...
src/arm64/macro-assembler-arm64.cc:449: // inserting set bits in the
least-significant bits.
On 2014/07/07 07:42:20, ulan wrote:
> Could you please add a comment explaining why we fill with set bits instead of
> zeros?

Done.

[m.m.capewell, 2014-07-07 13:31:31]

Committed patchset #2 manually as r22246 (presubmit successful).