Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(465)

Side by Side Diff: test/cctest/test-assembler-arm64.cc

Issue 364653003: ARM64: Reland faster immediate check (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 5 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch | Annotate | Revision Log
« no previous file with comments | « src/arm64/utils-arm64.cc ('k') | no next file » | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 408 matching lines...) Expand 10 before | Expand all | Expand 10 after
419 SETUP(); 419 SETUP();
420 420
421 START(); 421 START();
422 __ Mov(w0, 0xffffffffL); 422 __ Mov(w0, 0xffffffffL);
423 __ Mov(w1, 0xffff1234L); 423 __ Mov(w1, 0xffff1234L);
424 __ Mov(w2, 0x1234ffffL); 424 __ Mov(w2, 0x1234ffffL);
425 __ Mov(w3, 0x00000000L); 425 __ Mov(w3, 0x00000000L);
426 __ Mov(w4, 0x00001234L); 426 __ Mov(w4, 0x00001234L);
427 __ Mov(w5, 0x12340000L); 427 __ Mov(w5, 0x12340000L);
428 __ Mov(w6, 0x12345678L); 428 __ Mov(w6, 0x12345678L);
429 __ Mov(w7, (int32_t)0x80000000);
430 __ Mov(w8, (int32_t)0xffff0000);
431 __ Mov(w9, kWMinInt);
429 END(); 432 END();
430 433
431 RUN(); 434 RUN();
432 435
433 ASSERT_EQUAL_64(0xffffffffL, x0); 436 ASSERT_EQUAL_64(0xffffffffL, x0);
434 ASSERT_EQUAL_64(0xffff1234L, x1); 437 ASSERT_EQUAL_64(0xffff1234L, x1);
435 ASSERT_EQUAL_64(0x1234ffffL, x2); 438 ASSERT_EQUAL_64(0x1234ffffL, x2);
436 ASSERT_EQUAL_64(0x00000000L, x3); 439 ASSERT_EQUAL_64(0x00000000L, x3);
437 ASSERT_EQUAL_64(0x00001234L, x4); 440 ASSERT_EQUAL_64(0x00001234L, x4);
438 ASSERT_EQUAL_64(0x12340000L, x5); 441 ASSERT_EQUAL_64(0x12340000L, x5);
439 ASSERT_EQUAL_64(0x12345678L, x6); 442 ASSERT_EQUAL_64(0x12345678L, x6);
443 ASSERT_EQUAL_64(0x80000000L, x7);
444 ASSERT_EQUAL_64(0xffff0000L, x8);
445 ASSERT_EQUAL_32(kWMinInt, w9);
440 446
441 TEARDOWN(); 447 TEARDOWN();
442 } 448 }
443 449
444 450
445 TEST(mov_imm_x) { 451 TEST(mov_imm_x) {
446 INIT_V8(); 452 INIT_V8();
447 SETUP(); 453 SETUP();
448 454
449 START(); 455 START();
(...skipping 131 matching lines...) Expand 10 before | Expand all | Expand 10 after
581 TEST(bitwise_wide_imm) { 587 TEST(bitwise_wide_imm) {
582 INIT_V8(); 588 INIT_V8();
583 SETUP(); 589 SETUP();
584 590
585 START(); 591 START();
586 __ Mov(x0, 0); 592 __ Mov(x0, 0);
587 __ Mov(x1, 0xf0f0f0f0f0f0f0f0UL); 593 __ Mov(x1, 0xf0f0f0f0f0f0f0f0UL);
588 594
589 __ Orr(x10, x0, Operand(0x1234567890abcdefUL)); 595 __ Orr(x10, x0, Operand(0x1234567890abcdefUL));
590 __ Orr(w11, w1, Operand(0x90abcdef)); 596 __ Orr(w11, w1, Operand(0x90abcdef));
597
598 __ Orr(w12, w0, kWMinInt);
599 __ Eor(w13, w0, kWMinInt);
591 END(); 600 END();
592 601
593 RUN(); 602 RUN();
594 603
595 ASSERT_EQUAL_64(0, x0); 604 ASSERT_EQUAL_64(0, x0);
596 ASSERT_EQUAL_64(0xf0f0f0f0f0f0f0f0UL, x1); 605 ASSERT_EQUAL_64(0xf0f0f0f0f0f0f0f0UL, x1);
597 ASSERT_EQUAL_64(0x1234567890abcdefUL, x10); 606 ASSERT_EQUAL_64(0x1234567890abcdefUL, x10);
598 ASSERT_EQUAL_64(0xf0fbfdffUL, x11); 607 ASSERT_EQUAL_64(0xf0fbfdffUL, x11);
608 ASSERT_EQUAL_32(kWMinInt, w12);
609 ASSERT_EQUAL_32(kWMinInt, w13);
599 610
600 TEARDOWN(); 611 TEARDOWN();
601 } 612 }
602 613
603 614
604 TEST(orn) { 615 TEST(orn) {
605 INIT_V8(); 616 INIT_V8();
606 SETUP(); 617 SETUP();
607 618
608 START(); 619 START();
(...skipping 2746 matching lines...) Expand 10 before | Expand all | Expand 10 after
3355 START(); 3366 START();
3356 __ Mov(x0, 0x0); 3367 __ Mov(x0, 0x0);
3357 __ Mov(x1, 0x1); 3368 __ Mov(x1, 0x1);
3358 3369
3359 __ Add(x10, x0, Operand(0x1234567890abcdefUL)); 3370 __ Add(x10, x0, Operand(0x1234567890abcdefUL));
3360 __ Add(x11, x1, Operand(0xffffffff)); 3371 __ Add(x11, x1, Operand(0xffffffff));
3361 3372
3362 __ Add(w12, w0, Operand(0x12345678)); 3373 __ Add(w12, w0, Operand(0x12345678));
3363 __ Add(w13, w1, Operand(0xffffffff)); 3374 __ Add(w13, w1, Operand(0xffffffff));
3364 3375
3376 __ Add(w18, w0, Operand(kWMinInt));
3377 __ Sub(w19, w0, Operand(kWMinInt));
3378
3365 __ Sub(x20, x0, Operand(0x1234567890abcdefUL)); 3379 __ Sub(x20, x0, Operand(0x1234567890abcdefUL));
3366
3367 __ Sub(w21, w0, Operand(0x12345678)); 3380 __ Sub(w21, w0, Operand(0x12345678));
3368 END(); 3381 END();
3369 3382
3370 RUN(); 3383 RUN();
3371 3384
3372 ASSERT_EQUAL_64(0x1234567890abcdefUL, x10); 3385 ASSERT_EQUAL_64(0x1234567890abcdefUL, x10);
3373 ASSERT_EQUAL_64(0x100000000UL, x11); 3386 ASSERT_EQUAL_64(0x100000000UL, x11);
3374 3387
3375 ASSERT_EQUAL_32(0x12345678, w12); 3388 ASSERT_EQUAL_32(0x12345678, w12);
3376 ASSERT_EQUAL_64(0x0, x13); 3389 ASSERT_EQUAL_64(0x0, x13);
3377 3390
3391 ASSERT_EQUAL_32(kWMinInt, w18);
3392 ASSERT_EQUAL_32(kWMinInt, w19);
3393
3378 ASSERT_EQUAL_64(-0x1234567890abcdefUL, x20); 3394 ASSERT_EQUAL_64(-0x1234567890abcdefUL, x20);
3379
3380 ASSERT_EQUAL_32(-0x12345678, w21); 3395 ASSERT_EQUAL_32(-0x12345678, w21);
3381 3396
3382 TEARDOWN(); 3397 TEARDOWN();
3383 } 3398 }
3384 3399
3385 3400
3386 TEST(add_sub_shifted) { 3401 TEST(add_sub_shifted) {
3387 INIT_V8(); 3402 INIT_V8();
3388 SETUP(); 3403 SETUP();
3389 3404
(...skipping 7590 matching lines...) Expand 10 before | Expand all | Expand 10 after
10980 if (RelocInfo::IsVeneerPool(info->rmode())) { 10995 if (RelocInfo::IsVeneerPool(info->rmode())) {
10981 ASSERT(info->data() == veneer_pool_size); 10996 ASSERT(info->data() == veneer_pool_size);
10982 ++pool_count; 10997 ++pool_count;
10983 } 10998 }
10984 } 10999 }
10985 11000
10986 ASSERT(pool_count == 2); 11001 ASSERT(pool_count == 2);
10987 11002
10988 TEARDOWN(); 11003 TEARDOWN();
10989 } 11004 }
OLDNEW
« no previous file with comments | « src/arm64/utils-arm64.cc ('k') | no next file » | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698