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Side by Side Diff: src/mips/macro-assembler-mips.h

Issue 358363002: Move platform abstraction to base library (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: updates Created 6 years, 5 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
7 7
8 #include "src/assembler.h" 8 #include "src/assembler.h"
9 #include "src/globals.h" 9 #include "src/globals.h"
10 #include "src/mips/assembler-mips.h" 10 #include "src/mips/assembler-mips.h"
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706 void PushSafepointRegistersAndDoubles(); 706 void PushSafepointRegistersAndDoubles();
707 void PopSafepointRegistersAndDoubles(); 707 void PopSafepointRegistersAndDoubles();
708 // Store value in register src in the safepoint stack slot for 708 // Store value in register src in the safepoint stack slot for
709 // register dst. 709 // register dst.
710 void StoreToSafepointRegisterSlot(Register src, Register dst); 710 void StoreToSafepointRegisterSlot(Register src, Register dst);
711 void StoreToSafepointRegistersAndDoublesSlot(Register src, Register dst); 711 void StoreToSafepointRegistersAndDoublesSlot(Register src, Register dst);
712 // Load the value of the src register from its safepoint stack slot 712 // Load the value of the src register from its safepoint stack slot
713 // into register dst. 713 // into register dst.
714 void LoadFromSafepointRegisterSlot(Register dst, Register src); 714 void LoadFromSafepointRegisterSlot(Register dst, Register src);
715 715
716 // Flush the I-cache from asm code. You should use CPU::FlushICache from C. 716 // Flush the I-cache from asm code. You should use CpuFeatures::FlushICache
717 // from C.
717 // Does not handle errors. 718 // Does not handle errors.
718 void FlushICache(Register address, unsigned instructions); 719 void FlushICache(Register address, unsigned instructions);
719 720
720 // MIPS32 R2 instruction macro. 721 // MIPS32 R2 instruction macro.
721 void Ins(Register rt, Register rs, uint16_t pos, uint16_t size); 722 void Ins(Register rt, Register rs, uint16_t pos, uint16_t size);
722 void Ext(Register rt, Register rs, uint16_t pos, uint16_t size); 723 void Ext(Register rt, Register rs, uint16_t pos, uint16_t size);
723 724
724 // --------------------------------------------------------------------------- 725 // ---------------------------------------------------------------------------
725 // FPU macros. These do not handle special cases like NaN or +- inf. 726 // FPU macros. These do not handle special cases like NaN or +- inf.
726 727
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1688 #define CODE_COVERAGE_TOSTRING(x) CODE_COVERAGE_STRINGIFY(x) 1689 #define CODE_COVERAGE_TOSTRING(x) CODE_COVERAGE_STRINGIFY(x)
1689 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__) 1690 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
1690 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> 1691 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
1691 #else 1692 #else
1692 #define ACCESS_MASM(masm) masm-> 1693 #define ACCESS_MASM(masm) masm->
1693 #endif 1694 #endif
1694 1695
1695 } } // namespace v8::internal 1696 } } // namespace v8::internal
1696 1697
1697 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 1698 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
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