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Issue 358363002: Move platform abstraction to base library (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: updates Created 6 years, 5 months ago
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1 // Copyright 2006-2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 // This module contains the architecture-specific code. This make the rest of
6 // the code less dependent on differences between different processor
7 // architecture.
8 // The classes have the same definition for all architectures. The
9 // implementation for a particular architecture is put in cpu_<arch>.cc.
10 // The build system then uses the implementation for the target architecture.
11 //
12
13 #ifndef V8_CPU_H_
14 #define V8_CPU_H_
15
16 #include "src/allocation.h"
17
18 namespace v8 {
19 namespace internal {
20
21 // ----------------------------------------------------------------------------
22 // CPU
23 //
24 // Query information about the processor.
25 //
26 // This class also has static methods for the architecture specific functions.
27 // Add methods here to cope with differences between the supported
28 // architectures. For each architecture the file cpu_<arch>.cc contains the
29 // implementation of these static functions.
30
31 class CPU V8_FINAL BASE_EMBEDDED {
32 public:
33 CPU();
34
35 // x86 CPUID information
36 const char* vendor() const { return vendor_; }
37 int stepping() const { return stepping_; }
38 int model() const { return model_; }
39 int ext_model() const { return ext_model_; }
40 int family() const { return family_; }
41 int ext_family() const { return ext_family_; }
42 int type() const { return type_; }
43
44 // arm implementer/part information
45 int implementer() const { return implementer_; }
46 static const int ARM = 0x41;
47 static const int NVIDIA = 0x4e;
48 static const int QUALCOMM = 0x51;
49 int architecture() const { return architecture_; }
50 int part() const { return part_; }
51 static const int ARM_CORTEX_A5 = 0xc05;
52 static const int ARM_CORTEX_A7 = 0xc07;
53 static const int ARM_CORTEX_A8 = 0xc08;
54 static const int ARM_CORTEX_A9 = 0xc09;
55 static const int ARM_CORTEX_A12 = 0xc0c;
56 static const int ARM_CORTEX_A15 = 0xc0f;
57
58 // General features
59 bool has_fpu() const { return has_fpu_; }
60
61 // x86 features
62 bool has_cmov() const { return has_cmov_; }
63 bool has_sahf() const { return has_sahf_; }
64 bool has_mmx() const { return has_mmx_; }
65 bool has_sse() const { return has_sse_; }
66 bool has_sse2() const { return has_sse2_; }
67 bool has_sse3() const { return has_sse3_; }
68 bool has_ssse3() const { return has_ssse3_; }
69 bool has_sse41() const { return has_sse41_; }
70 bool has_sse42() const { return has_sse42_; }
71
72 // arm features
73 bool has_idiva() const { return has_idiva_; }
74 bool has_neon() const { return has_neon_; }
75 bool has_thumb2() const { return has_thumb2_; }
76 bool has_vfp() const { return has_vfp_; }
77 bool has_vfp3() const { return has_vfp3_; }
78 bool has_vfp3_d32() const { return has_vfp3_d32_; }
79
80 // Flush instruction cache.
81 static void FlushICache(void* start, size_t size);
82
83 private:
84 char vendor_[13];
85 int stepping_;
86 int model_;
87 int ext_model_;
88 int family_;
89 int ext_family_;
90 int type_;
91 int implementer_;
92 int architecture_;
93 int part_;
94 bool has_fpu_;
95 bool has_cmov_;
96 bool has_sahf_;
97 bool has_mmx_;
98 bool has_sse_;
99 bool has_sse2_;
100 bool has_sse3_;
101 bool has_ssse3_;
102 bool has_sse41_;
103 bool has_sse42_;
104 bool has_idiva_;
105 bool has_neon_;
106 bool has_thumb2_;
107 bool has_vfp_;
108 bool has_vfp3_;
109 bool has_vfp3_d32_;
110 };
111
112 } } // namespace v8::internal
113
114 #endif // V8_CPU_H_
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