Move platform abstraction to base library

src/base/cpu.h

 // Copyright 2006-2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // This module contains the architecture-specific code. This make the rest of
 // the code less dependent on differences between different processor
 // architecture.
 // The classes have the same definition for all architectures. The
 // implementation for a particular architecture is put in cpu_<arch>.cc.
 // The build system then uses the implementation for the target architecture.
 //
 
-#ifndef V8_CPU_H_
-#define V8_CPU_H_
+#ifndef V8_BASE_CPU_H_
+#define V8_BASE_CPU_H_
 
-#include "src/allocation.h"
+#include "src/base/macros.h"
 
 namespace v8 {
-namespace internal {
+namespace base {
 
 // ----------------------------------------------------------------------------
 // CPU
 //
 // Query information about the processor.
 //
 // This class also has static methods for the architecture specific functions.
 // Add methods here to cope with differences between the supported
 // architectures. For each architecture the file cpu_<arch>.cc contains the
 // implementation of these static functions.
 
-class CPU V8_FINAL BASE_EMBEDDED {
+class CPU V8_FINAL {
  public:
   CPU();
 
   // x86 CPUID information
   const char* vendor() const { return vendor_; }
   int stepping() const { return stepping_; }
   int model() const { return model_; }
   int ext_model() const { return ext_model_; }
   int family() const { return family_; }
   int ext_family() const { return ext_family_; }
   int type() const { return type_; }
 
   // arm implementer/part information
   int implementer() const { return implementer_; }
   static const int ARM = 0x41;

[tfarina, 2014/07/01 15:58:30]

we could group these 'static const' before the ctor per style guide.

and maybe turn it in an enum to avoid the repetition of 'static const int'

   static const int NVIDIA = 0x4e;
   static const int QUALCOMM = 0x51;
   int architecture() const { return architecture_; }
   int part() const { return part_; }
   static const int ARM_CORTEX_A5 = 0xc05;
   static const int ARM_CORTEX_A7 = 0xc07;
   static const int ARM_CORTEX_A8 = 0xc08;
   static const int ARM_CORTEX_A9 = 0xc09;
   static const int ARM_CORTEX_A12 = 0xc0c;
   static const int ARM_CORTEX_A15 = 0xc0f;
@@ skipping 13 matching lines @@
   bool has_sse42() const { return has_sse42_; }
 
   // arm features
   bool has_idiva() const { return has_idiva_; }
   bool has_neon() const { return has_neon_; }
   bool has_thumb2() const { return has_thumb2_; }
   bool has_vfp() const { return has_vfp_; }
   bool has_vfp3() const { return has_vfp3_; }
   bool has_vfp3_d32() const { return has_vfp3_d32_; }
 
-  // Flush instruction cache.
-  static void FlushICache(void* start, size_t size);
-
  private:
   char vendor_[13];
   int stepping_;
   int model_;
   int ext_model_;
   int family_;
   int ext_family_;
   int type_;
   int implementer_;
   int architecture_;
   int part_;
   bool has_fpu_;
   bool has_cmov_;
   bool has_sahf_;
   bool has_mmx_;
   bool has_sse_;
   bool has_sse2_;
   bool has_sse3_;
   bool has_ssse3_;
   bool has_sse41_;
   bool has_sse42_;
   bool has_idiva_;
   bool has_neon_;
   bool has_thumb2_;
   bool has_vfp_;
   bool has_vfp3_;
   bool has_vfp3_d32_;
 };
 
-} }  // namespace v8::internal
+} }  // namespace v8::base
 
-#endif  // V8_CPU_H_
+#endif  // V8_BASE_CPU_H_