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Side by Side Diff: src/arm64/cpu-arm64.cc

Issue 358363002: Move platform abstraction to base library (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: updates Created 6 years, 5 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // CPU specific code for arm independent of OS goes here. 5 // CPU specific code for arm independent of OS goes here.
6 6
7 #include "src/v8.h" 7 #include "src/v8.h"
8 8
9 #if V8_TARGET_ARCH_ARM64 9 #if V8_TARGET_ARCH_ARM64
10 10
11 #include "src/arm64/utils-arm64.h" 11 #include "src/arm64/utils-arm64.h"
12 #include "src/cpu.h" 12 #include "src/assembler.h"
13 13
14 namespace v8 { 14 namespace v8 {
15 namespace internal { 15 namespace internal {
16 16
17 class CacheLineSizes { 17 class CacheLineSizes {
18 public: 18 public:
19 CacheLineSizes() { 19 CacheLineSizes() {
20 #ifdef USE_SIMULATOR 20 #ifdef USE_SIMULATOR
21 cache_type_register_ = 0; 21 cache_type_register_ = 0;
22 #else 22 #else
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33 uint32_t ExtractCacheLineSize(int cache_line_size_shift) const { 33 uint32_t ExtractCacheLineSize(int cache_line_size_shift) const {
34 // The cache type register holds the size of cache lines in words as a 34 // The cache type register holds the size of cache lines in words as a
35 // power of two. 35 // power of two.
36 return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf); 36 return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf);
37 } 37 }
38 38
39 uint32_t cache_type_register_; 39 uint32_t cache_type_register_;
40 }; 40 };
41 41
42 42
43 void CPU::FlushICache(void* address, size_t length) { 43 void CpuFeatures::FlushICache(void* address, size_t length) {
44 if (length == 0) return; 44 if (length == 0) return;
45 45
46 #ifdef USE_SIMULATOR 46 #ifdef USE_SIMULATOR
47 // TODO(all): consider doing some cache simulation to ensure every address 47 // TODO(all): consider doing some cache simulation to ensure every address
48 // run has been synced. 48 // run has been synced.
49 USE(address); 49 USE(address);
50 USE(length); 50 USE(length);
51 #else 51 #else
52 // The code below assumes user space cache operations are allowed. The goal 52 // The code below assumes user space cache operations are allowed. The goal
53 // of this routine is to make sure the code generated is visible to the I 53 // of this routine is to make sure the code generated is visible to the I
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114 // This code does not write to memory but without the dependency gcc might 114 // This code does not write to memory but without the dependency gcc might
115 // move this code before the code is generated. 115 // move this code before the code is generated.
116 : "cc", "memory" 116 : "cc", "memory"
117 ); // NOLINT 117 ); // NOLINT
118 #endif 118 #endif
119 } 119 }
120 120
121 } } // namespace v8::internal 121 } } // namespace v8::internal
122 122
123 #endif // V8_TARGET_ARCH_ARM64 123 #endif // V8_TARGET_ARCH_ARM64
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