| OLD | NEW |
| 1 /* | 1 /* |
| 2 * Copyright 2014 The Android Open Source Project | 2 * Copyright 2014 The Android Open Source Project |
| 3 * | 3 * |
| 4 * Use of this source code is governed by a BSD-style license that can be | 4 * Use of this source code is governed by a BSD-style license that can be |
| 5 * found in the LICENSE file. | 5 * found in the LICENSE file. |
| 6 */ | 6 */ |
| 7 | 7 |
| 8 #include "SkBlitRow.h" | 8 #include "SkBlitRow.h" |
| 9 #include "SkBlitMask.h" | 9 #include "SkBlitMask.h" |
| 10 #include "SkColorPriv.h" | 10 #include "SkColorPriv.h" |
| (...skipping 16 matching lines...) Expand all Loading... |
| 27 "repl.ph %[s5], 0x1f \n\t" | 27 "repl.ph %[s5], 0x1f \n\t" |
| 28 "repl.ph %[s6], 0x3f \n\t" | 28 "repl.ph %[s6], 0x3f \n\t" |
| 29 "1: \n\t" | 29 "1: \n\t" |
| 30 "lw %[s2], 0(%[src]) \n\t" | 30 "lw %[s2], 0(%[src]) \n\t" |
| 31 "lw %[s1], 4(%[src]) \n\t" | 31 "lw %[s1], 4(%[src]) \n\t" |
| 32 "lwr %[s0], 0(%[dst]) \n\t" | 32 "lwr %[s0], 0(%[dst]) \n\t" |
| 33 "lwl %[s0], 3(%[dst]) \n\t" | 33 "lwl %[s0], 3(%[dst]) \n\t" |
| 34 "and %[t1], %[s0], %[s5] \n\t" | 34 "and %[t1], %[s0], %[s5] \n\t" |
| 35 "shra.ph %[t0], %[s0], 5 \n\t" | 35 "shra.ph %[t0], %[s0], 5 \n\t" |
| 36 "and %[t2], %[t0], %[s6] \n\t" | 36 "and %[t2], %[t0], %[s6] \n\t" |
| 37 #ifdef __MIPS_HAVE_DSPR2 | 37 #ifdef SK_MIPS_HAS_DSPR2 |
| 38 "shrl.ph %[t3], %[s0], 11 \n\t" | 38 "shrl.ph %[t3], %[s0], 11 \n\t" |
| 39 #else | 39 #else |
| 40 "shra.ph %[t0], %[s0], 11 \n\t" | 40 "shra.ph %[t0], %[s0], 11 \n\t" |
| 41 "and %[t3], %[t0], %[s5] \n\t" | 41 "and %[t3], %[t0], %[s5] \n\t" |
| 42 #endif | 42 #endif |
| 43 "precrq.ph.w %[t0], %[s1], %[s2] \n\t" | 43 "precrq.ph.w %[t0], %[s1], %[s2] \n\t" |
| 44 "shrl.qb %[t5], %[t0], 3 \n\t" | 44 "shrl.qb %[t5], %[t0], 3 \n\t" |
| 45 "and %[t4], %[t5], %[s5] \n\t" | 45 "and %[t4], %[t5], %[s5] \n\t" |
| 46 "ins %[s2], %[s1], 16, 16 \n\t" | 46 "ins %[s2], %[s1], 16, 16 \n\t" |
| 47 "preceu.ph.qbra %[t0], %[s2] \n\t" | 47 "preceu.ph.qbra %[t0], %[s2] \n\t" |
| 48 "shrl.qb %[t6], %[t0], 3 \n\t" | 48 "shrl.qb %[t6], %[t0], 3 \n\t" |
| 49 #ifdef __MIPS_HAVE_DSPR2 | 49 #ifdef SK_MIPS_HAS_DSPR2 |
| 50 "shrl.ph %[t5], %[s2], 10 \n\t" | 50 "shrl.ph %[t5], %[s2], 10 \n\t" |
| 51 #else | 51 #else |
| 52 "shra.ph %[t0], %[s2], 10 \n\t" | 52 "shra.ph %[t0], %[s2], 10 \n\t" |
| 53 "and %[t5], %[t0], %[s6] \n\t" | 53 "and %[t5], %[t0], %[s6] \n\t" |
| 54 #endif | 54 #endif |
| 55 "subu.qb %[t4], %[t4], %[t1] \n\t" | 55 "subu.qb %[t4], %[t4], %[t1] \n\t" |
| 56 "subu.qb %[t5], %[t5], %[t2] \n\t" | 56 "subu.qb %[t5], %[t5], %[t2] \n\t" |
| 57 "subu.qb %[t6], %[t6], %[t3] \n\t" | 57 "subu.qb %[t6], %[t6], %[t3] \n\t" |
| 58 "muleu_s.ph.qbr %[t4], %[s4], %[t4] \n\t" | 58 "muleu_s.ph.qbr %[t4], %[s4], %[t4] \n\t" |
| 59 "muleu_s.ph.qbr %[t5], %[s4], %[t5] \n\t" | 59 "muleu_s.ph.qbr %[t5], %[s4], %[t5] \n\t" |
| (...skipping 236 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 296 "lw %[t0], 8(%[dither]) \n\t" | 296 "lw %[t0], 8(%[dither]) \n\t" |
| 297 "lw %[t1], 12(%[dither]) \n\t" | 297 "lw %[t1], 12(%[dither]) \n\t" |
| 298 "li %[s0], 1 \n\t" | 298 "li %[s0], 1 \n\t" |
| 299 "4: \n\t" | 299 "4: \n\t" |
| 300 "sll %[t2], %[t0], 16 \n\t" | 300 "sll %[t2], %[t0], 16 \n\t" |
| 301 "or %[t1], %[t2], %[t1] \n\t" | 301 "or %[t1], %[t2], %[t1] \n\t" |
| 302 "lw %[t0], 0(%[src]) \n\t" | 302 "lw %[t0], 0(%[src]) \n\t" |
| 303 "lw %[t2], 4(%[src]) \n\t" | 303 "lw %[t2], 4(%[src]) \n\t" |
| 304 "precrq.ph.w %[t3], %[t0], %[t2] \n\t" | 304 "precrq.ph.w %[t3], %[t0], %[t2] \n\t" |
| 305 "preceu.ph.qbra %[t9], %[t3] \n\t" | 305 "preceu.ph.qbra %[t9], %[t3] \n\t" |
| 306 #ifdef __MIPS_HAVE_DSPR2 | 306 #ifdef SK_MIPS_HAS_DSPR2 |
| 307 "append %[t0], %[t2], 16 \n\t" | 307 "append %[t0], %[t2], 16 \n\t" |
| 308 "preceu.ph.qbra %[t4], %[t0] \n\t" | 308 "preceu.ph.qbra %[t4], %[t0] \n\t" |
| 309 "preceu.ph.qbla %[t5], %[t0] \n\t" | 309 "preceu.ph.qbla %[t5], %[t0] \n\t" |
| 310 #else | 310 #else |
| 311 "sll %[t6], %[t0], 16 \n\t" | 311 "sll %[t6], %[t0], 16 \n\t" |
| 312 "sll %[t7], %[t2], 16 \n\t" | 312 "sll %[t7], %[t2], 16 \n\t" |
| 313 "precrq.ph.w %[t8], %[t6], %[t7] \n\t" | 313 "precrq.ph.w %[t8], %[t6], %[t7] \n\t" |
| 314 "preceu.ph.qbra %[t4], %[t8] \n\t" | 314 "preceu.ph.qbra %[t4], %[t8] \n\t" |
| 315 "preceu.ph.qbla %[t5], %[t8] \n\t" | 315 "preceu.ph.qbla %[t5], %[t8] \n\t" |
| 316 #endif | 316 #endif |
| 317 "addu.qb %[t0], %[t4], %[t1] \n\t" | 317 "addu.qb %[t0], %[t4], %[t1] \n\t" |
| 318 "shra.ph %[t2], %[t4], 5 \n\t" | 318 "shra.ph %[t2], %[t4], 5 \n\t" |
| 319 "subu.qb %[t3], %[t0], %[t2] \n\t" | 319 "subu.qb %[t3], %[t0], %[t2] \n\t" |
| 320 "shra.ph %[t6], %[t3], 3 \n\t" | 320 "shra.ph %[t6], %[t3], 3 \n\t" |
| 321 "addu.qb %[t0], %[t9], %[t1] \n\t" | 321 "addu.qb %[t0], %[t9], %[t1] \n\t" |
| 322 "shra.ph %[t2], %[t9], 5 \n\t" | 322 "shra.ph %[t2], %[t9], 5 \n\t" |
| 323 "subu.qb %[t3], %[t0], %[t2] \n\t" | 323 "subu.qb %[t3], %[t0], %[t2] \n\t" |
| 324 "shra.ph %[t7], %[t3], 3 \n\t" | 324 "shra.ph %[t7], %[t3], 3 \n\t" |
| 325 "shra.ph %[t0], %[t1], 1 \n\t" | 325 "shra.ph %[t0], %[t1], 1 \n\t" |
| 326 "shra.ph %[t2], %[t5], 6 \n\t" | 326 "shra.ph %[t2], %[t5], 6 \n\t" |
| 327 "addu.qb %[t3], %[t5], %[t0] \n\t" | 327 "addu.qb %[t3], %[t5], %[t0] \n\t" |
| 328 "subu.qb %[t4], %[t3], %[t2] \n\t" | 328 "subu.qb %[t4], %[t3], %[t2] \n\t" |
| 329 "shra.ph %[t8], %[t4], 2 \n\t" | 329 "shra.ph %[t8], %[t4], 2 \n\t" |
| 330 "precrq.ph.w %[t0], %[t6], %[t7] \n\t" | 330 "precrq.ph.w %[t0], %[t6], %[t7] \n\t" |
| 331 #ifdef __MIPS_HAVE_DSPR2 | 331 #ifdef SK_MIPS_HAS_DSPR2 |
| 332 "append %[t6], %[t7], 16 \n\t" | 332 "append %[t6], %[t7], 16 \n\t" |
| 333 #else | 333 #else |
| 334 "sll %[t6], %[t6], 16 \n\t" | 334 "sll %[t6], %[t6], 16 \n\t" |
| 335 "sll %[t2], %[t7], 16 \n\t" | 335 "sll %[t2], %[t7], 16 \n\t" |
| 336 "precrq.ph.w %[t6], %[t6], %[t2] \n\t" | 336 "precrq.ph.w %[t6], %[t6], %[t2] \n\t" |
| 337 #endif | 337 #endif |
| 338 "sra %[t4], %[t8], 16 \n\t" | 338 "sra %[t4], %[t8], 16 \n\t" |
| 339 "andi %[t5], %[t8], 0xFF \n\t" | 339 "andi %[t5], %[t8], 0xFF \n\t" |
| 340 "sll %[t7], %[t4], 5 \n\t" | 340 "sll %[t7], %[t4], 5 \n\t" |
| 341 "sra %[t8], %[t0], 5 \n\t" | 341 "sra %[t8], %[t0], 5 \n\t" |
| (...skipping 76 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 418 "li %[x1], 1 \n\t" | 418 "li %[x1], 1 \n\t" |
| 419 "b 5f \n\t" | 419 "b 5f \n\t" |
| 420 " nop \n\t" | 420 " nop \n\t" |
| 421 "4: \n\t" | 421 "4: \n\t" |
| 422 "lw %[t0], 8(%[dither]) \n\t" | 422 "lw %[t0], 8(%[dither]) \n\t" |
| 423 "lw %[t1], 12(%[dither]) \n\t" | 423 "lw %[t1], 12(%[dither]) \n\t" |
| 424 "li %[x1], 0 \n\t" | 424 "li %[x1], 0 \n\t" |
| 425 "5: \n\t" | 425 "5: \n\t" |
| 426 "sll %[t3], %[t0], 7 \n\t" | 426 "sll %[t3], %[t0], 7 \n\t" |
| 427 "sll %[t4], %[t1], 7 \n\t" | 427 "sll %[t4], %[t1], 7 \n\t" |
| 428 #ifdef __MIPS_HAVE_DSPR2 | 428 #ifdef SK_MIPS_HAS_DSPR2 |
| 429 "append %[t0], %[t1], 16 \n\t" | 429 "append %[t0], %[t1], 16 \n\t" |
| 430 #else | 430 #else |
| 431 "sll %[t0], %[t0], 8 \n\t" | 431 "sll %[t0], %[t0], 8 \n\t" |
| 432 "sll %[t2], %[t1], 8 \n\t" | 432 "sll %[t2], %[t1], 8 \n\t" |
| 433 "precrq.qb.ph %[t0], %[t0], %[t2] \n\t" | 433 "precrq.qb.ph %[t0], %[t0], %[t2] \n\t" |
| 434 #endif | 434 #endif |
| 435 "precrq.qb.ph %[t1], %[t3], %[t4] \n\t" | 435 "precrq.qb.ph %[t1], %[t3], %[t4] \n\t" |
| 436 "sll %[t5], %[s0], 8 \n\t" | 436 "sll %[t5], %[s0], 8 \n\t" |
| 437 "sll %[t6], %[s1], 8 \n\t" | 437 "sll %[t6], %[s1], 8 \n\t" |
| 438 "precrq.qb.ph %[t4], %[t5], %[t6] \n\t" | 438 "precrq.qb.ph %[t4], %[t5], %[t6] \n\t" |
| 439 "precrq.qb.ph %[t6], %[s0], %[s1] \n\t" | 439 "precrq.qb.ph %[t6], %[s0], %[s1] \n\t" |
| 440 "preceu.ph.qbla %[t5], %[t4] \n\t" | 440 "preceu.ph.qbla %[t5], %[t4] \n\t" |
| 441 "preceu.ph.qbra %[t4], %[t4] \n\t" | 441 "preceu.ph.qbra %[t4], %[t4] \n\t" |
| 442 "preceu.ph.qbra %[t6], %[t6] \n\t" | 442 "preceu.ph.qbra %[t6], %[t6] \n\t" |
| 443 "lh %[t2], 0(%[dst]) \n\t" | 443 "lh %[t2], 0(%[dst]) \n\t" |
| 444 "lh %[s1], 2(%[dst]) \n\t" | 444 "lh %[s1], 2(%[dst]) \n\t" |
| 445 #ifdef __MIPS_HAVE_DSPR2 | 445 #ifdef SK_MIPS_HAS_DSPR2 |
| 446 "append %[t2], %[s1], 16 \n\t" | 446 "append %[t2], %[s1], 16 \n\t" |
| 447 #else | 447 #else |
| 448 "sll %[s1], %[s1], 16 \n\t" | 448 "sll %[s1], %[s1], 16 \n\t" |
| 449 "packrl.ph %[t2], %[t2], %[s1] \n\t" | 449 "packrl.ph %[t2], %[t2], %[s1] \n\t" |
| 450 #endif | 450 #endif |
| 451 "shra.ph %[s1], %[t2], 11 \n\t" | 451 "shra.ph %[s1], %[t2], 11 \n\t" |
| 452 "and %[s1], %[s1], 0x1F001F \n\t" | 452 "and %[s1], %[s1], 0x1F001F \n\t" |
| 453 "shra.ph %[s2], %[t2], 5 \n\t" | 453 "shra.ph %[s2], %[t2], 5 \n\t" |
| 454 "and %[s2], %[s2], 0x3F003F \n\t" | 454 "and %[s2], %[s2], 0x3F003F \n\t" |
| 455 "and %[s3], %[t2], 0x1F001F \n\t" | 455 "and %[s3], %[t2], 0x1F001F \n\t" |
| (...skipping 112 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 568 " nop \n\t" | 568 " nop \n\t" |
| 569 "li %[t16], 2 \n\t" | 569 "li %[t16], 2 \n\t" |
| 570 "pref 0, 64(%[src]) \n\t" | 570 "pref 0, 64(%[src]) \n\t" |
| 571 "pref 1, 64(%[dst]) \n\t" | 571 "pref 1, 64(%[dst]) \n\t" |
| 572 "3: \n\t" | 572 "3: \n\t" |
| 573 "addiu %[t16], %[t16], -1 \n\t" | 573 "addiu %[t16], %[t16], -1 \n\t" |
| 574 "lw %[t0], 0(%[src]) \n\t" | 574 "lw %[t0], 0(%[src]) \n\t" |
| 575 "lw %[t1], 4(%[src]) \n\t" | 575 "lw %[t1], 4(%[src]) \n\t" |
| 576 "precrq.ph.w %[t2], %[t0], %[t1] \n\t" | 576 "precrq.ph.w %[t2], %[t0], %[t1] \n\t" |
| 577 "preceu.ph.qbra %[t8], %[t2] \n\t" | 577 "preceu.ph.qbra %[t8], %[t2] \n\t" |
| 578 #ifdef __MIPS_HAVE_DSPR2 | 578 #ifdef SK_MIPS_HAS_DSPR2 |
| 579 "append %[t0], %[t1], 16 \n\t" | 579 "append %[t0], %[t1], 16 \n\t" |
| 580 #else | 580 #else |
| 581 "sll %[t0], %[t0], 16 \n\t" | 581 "sll %[t0], %[t0], 16 \n\t" |
| 582 "sll %[t6], %[t1], 16 \n\t" | 582 "sll %[t6], %[t1], 16 \n\t" |
| 583 "precrq.ph.w %[t0], %[t0], %[t6] \n\t" | 583 "precrq.ph.w %[t0], %[t0], %[t6] \n\t" |
| 584 #endif | 584 #endif |
| 585 "preceu.ph.qbra %[t3], %[t0] \n\t" | 585 "preceu.ph.qbra %[t3], %[t0] \n\t" |
| 586 "preceu.ph.qbla %[t4], %[t0] \n\t" | 586 "preceu.ph.qbla %[t4], %[t0] \n\t" |
| 587 "preceu.ph.qbla %[t0], %[t2] \n\t" | 587 "preceu.ph.qbla %[t0], %[t2] \n\t" |
| 588 "subq.ph %[t1], %[sa], %[t0] \n\t" | 588 "subq.ph %[t1], %[sa], %[t0] \n\t" |
| 589 "sra %[t2], %[t1], 8 \n\t" | 589 "sra %[t2], %[t1], 8 \n\t" |
| 590 "or %[t5], %[t2], %[t1] \n\t" | 590 "or %[t5], %[t2], %[t1] \n\t" |
| 591 "replv.ph %[t2], %[t5] \n\t" | 591 "replv.ph %[t2], %[t5] \n\t" |
| 592 "lh %[t0], 0(%[dst]) \n\t" | 592 "lh %[t0], 0(%[dst]) \n\t" |
| 593 "lh %[t1], 2(%[dst]) \n\t" | 593 "lh %[t1], 2(%[dst]) \n\t" |
| 594 "and %[t1], %[t1], 0xffff \n\t" | 594 "and %[t1], %[t1], 0xffff \n\t" |
| 595 #ifdef __MIPS_HAVE_DSPR2 | 595 #ifdef SK_MIPS_HAS_DSPR2 |
| 596 "append %[t0], %[t1], 16 \n\t" | 596 "append %[t0], %[t1], 16 \n\t" |
| 597 #else | 597 #else |
| 598 "sll %[t5], %[t0], 16 \n\t" | 598 "sll %[t5], %[t0], 16 \n\t" |
| 599 "or %[t0], %[t5], %[t1] \n\t" | 599 "or %[t0], %[t5], %[t1] \n\t" |
| 600 #endif | 600 #endif |
| 601 "and %[t1], %[t0], 0x1f001f \n\t" | 601 "and %[t1], %[t0], 0x1f001f \n\t" |
| 602 "shra.ph %[t6], %[t0], 11 \n\t" | 602 "shra.ph %[t6], %[t0], 11 \n\t" |
| 603 "and %[t6], %[t6], 0x1f001f \n\t" | 603 "and %[t6], %[t6], 0x1f001f \n\t" |
| 604 "and %[t7], %[t0], 0x7e007e0 \n\t" | 604 "and %[t7], %[t0], 0x7e007e0 \n\t" |
| 605 "shra.ph %[t5], %[t7], 5 \n\t" | 605 "shra.ph %[t5], %[t7], 5 \n\t" |
| (...skipping 195 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 801 "2: \n\t" | 801 "2: \n\t" |
| 802 ".set pop \n\t" | 802 ".set pop \n\t" |
| 803 : [src]"+r"(src), [dst]"+r"(dst), [count]"+r"(count), | 803 : [src]"+r"(src), [dst]"+r"(dst), [count]"+r"(count), |
| 804 [t0]"=&r"(t0), [t1]"=&r"(t1), [t2]"=&r"(t2), [t3]"=&r"(t3), | 804 [t0]"=&r"(t0), [t1]"=&r"(t1), [t2]"=&r"(t2), [t3]"=&r"(t3), |
| 805 [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6), [t7]"=&r"(t7) | 805 [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6), [t7]"=&r"(t7) |
| 806 : [alpha]"r"(alpha) | 806 : [alpha]"r"(alpha) |
| 807 : "memory", "hi", "lo" | 807 : "memory", "hi", "lo" |
| 808 ); | 808 ); |
| 809 } | 809 } |
| 810 | 810 |
| 811 void blitmask_d565_opaque_mips(int width, int height, uint16_t* device, |
| 812 unsigned deviceRB, const uint8_t* alpha, |
| 813 uint32_t expanded32, unsigned maskRB) { |
| 814 register uint32_t s0, s1, s2, s3; |
| 815 |
| 816 __asm__ volatile ( |
| 817 ".set push \n\t" |
| 818 ".set noreorder \n\t" |
| 819 ".set noat \n\t" |
| 820 "li $t9, 0x7E0F81F \n\t" |
| 821 "1: \n\t" |
| 822 "move $t8, %[width] \n\t" |
| 823 "addiu %[height], %[height], -1 \n\t" |
| 824 "2: \n\t" |
| 825 "beqz $t8, 4f \n\t" |
| 826 " addiu $t0, $t8, -4 \n\t" |
| 827 "bltz $t0, 3f \n\t" |
| 828 " nop \n\t" |
| 829 "addiu $t8, $t8, -4 \n\t" |
| 830 "lhu $t0, 0(%[device]) \n\t" |
| 831 "lhu $t1, 2(%[device]) \n\t" |
| 832 "lhu $t2, 4(%[device]) \n\t" |
| 833 "lhu $t3, 6(%[device]) \n\t" |
| 834 "lbu $t4, 0(%[alpha]) \n\t" |
| 835 "lbu $t5, 1(%[alpha]) \n\t" |
| 836 "lbu $t6, 2(%[alpha]) \n\t" |
| 837 "lbu $t7, 3(%[alpha]) \n\t" |
| 838 "replv.ph $t0, $t0 \n\t" |
| 839 "replv.ph $t1, $t1 \n\t" |
| 840 "replv.ph $t2, $t2 \n\t" |
| 841 "replv.ph $t3, $t3 \n\t" |
| 842 "addiu %[s0], $t4, 1 \n\t" |
| 843 "addiu %[s1], $t5, 1 \n\t" |
| 844 "addiu %[s2], $t6, 1 \n\t" |
| 845 "addiu %[s3], $t7, 1 \n\t" |
| 846 "srl %[s0], %[s0], 3 \n\t" |
| 847 "srl %[s1], %[s1], 3 \n\t" |
| 848 "srl %[s2], %[s2], 3 \n\t" |
| 849 "srl %[s3], %[s3], 3 \n\t" |
| 850 "and $t0, $t0, $t9 \n\t" |
| 851 "and $t1, $t1, $t9 \n\t" |
| 852 "and $t2, $t2, $t9 \n\t" |
| 853 "and $t3, $t3, $t9 \n\t" |
| 854 "subu $t4, %[expanded32], $t0 \n\t" |
| 855 "subu $t5, %[expanded32], $t1 \n\t" |
| 856 "subu $t6, %[expanded32], $t2 \n\t" |
| 857 "subu $t7, %[expanded32], $t3 \n\t" |
| 858 "mul $t4, $t4, %[s0] \n\t" |
| 859 "mul $t5, $t5, %[s1] \n\t" |
| 860 "mul $t6, $t6, %[s2] \n\t" |
| 861 "mul $t7, $t7, %[s3] \n\t" |
| 862 "addiu %[alpha], %[alpha], 4 \n\t" |
| 863 "srl $t4, $t4, 5 \n\t" |
| 864 "srl $t5, $t5, 5 \n\t" |
| 865 "srl $t6, $t6, 5 \n\t" |
| 866 "srl $t7, $t7, 5 \n\t" |
| 867 "addu $t4, $t0, $t4 \n\t" |
| 868 "addu $t5, $t1, $t5 \n\t" |
| 869 "addu $t6, $t2, $t6 \n\t" |
| 870 "addu $t7, $t3, $t7 \n\t" |
| 871 "and $t4, $t4, $t9 \n\t" |
| 872 "and $t5, $t5, $t9 \n\t" |
| 873 "and $t6, $t6, $t9 \n\t" |
| 874 "and $t7, $t7, $t9 \n\t" |
| 875 "srl $t0, $t4, 16 \n\t" |
| 876 "srl $t1, $t5, 16 \n\t" |
| 877 "srl $t2, $t6, 16 \n\t" |
| 878 "srl $t3, $t7, 16 \n\t" |
| 879 "or %[s0], $t0, $t4 \n\t" |
| 880 "or %[s1], $t1, $t5 \n\t" |
| 881 "or %[s2], $t2, $t6 \n\t" |
| 882 "or %[s3], $t3, $t7 \n\t" |
| 883 "sh %[s0], 0(%[device]) \n\t" |
| 884 "sh %[s1], 2(%[device]) \n\t" |
| 885 "sh %[s2], 4(%[device]) \n\t" |
| 886 "sh %[s3], 6(%[device]) \n\t" |
| 887 "b 2b \n\t" |
| 888 " addiu %[device], %[device], 8 \n\t" |
| 889 "3: \n\t" |
| 890 "lhu $t0, 0(%[device]) \n\t" |
| 891 "lbu $t1, 0(%[alpha]) \n\t" |
| 892 "addiu $t8, $t8, -1 \n\t" |
| 893 "replv.ph $t2, $t0 \n\t" |
| 894 "and $t2, $t2, $t9 \n\t" |
| 895 "addiu $t0, $t1, 1 \n\t" |
| 896 "srl $t0, $t0, 3 \n\t" |
| 897 "subu $t3, %[expanded32], $t2 \n\t" |
| 898 "mul $t3, $t3, $t0 \n\t" |
| 899 "addiu %[alpha], %[alpha], 1 \n\t" |
| 900 "srl $t3, $t3, 5 \n\t" |
| 901 "addu $t3, $t2, $t3 \n\t" |
| 902 "and $t3, $t3, $t9 \n\t" |
| 903 "srl $t4, $t3, 16 \n\t" |
| 904 "or %[s0], $t4, $t3 \n\t" |
| 905 "sh %[s0], 0(%[device]) \n\t" |
| 906 "bnez $t8, 3b \n\t" |
| 907 "addiu %[device], %[device], 2 \n\t" |
| 908 "4: \n\t" |
| 909 "addu %[device], %[device], %[deviceRB] \n\t" |
| 910 "bgtz %[height], 1b \n\t" |
| 911 " addu %[alpha], %[alpha], %[maskRB] \n\t" |
| 912 ".set pop \n\t" |
| 913 : [height]"+r"(height), [alpha]"+r"(alpha), [device]"+r"(device), |
| 914 [deviceRB]"+r"(deviceRB), [maskRB]"+r"(maskRB), [s0]"=&r"(s0), |
| 915 [s1]"=&r"(s1), [s2]"=&r"(s2), [s3]"=&r"(s3) |
| 916 : [expanded32] "r" (expanded32), [width] "r" (width) |
| 917 : "memory", "hi", "lo", "t0", "t1", "t2", "t3", |
| 918 "t4", "t5", "t6", "t7", "t8", "t9" |
| 919 ); |
| 920 } |
| 921 |
| 811 ////////////////////////////////////////////////////////////////////////////////
/////////////////// | 922 ////////////////////////////////////////////////////////////////////////////////
/////////////////// |
| 812 | 923 |
| 813 const SkBlitRow::Proc platform_565_procs_mips_dsp[] = { | 924 const SkBlitRow::Proc platform_565_procs_mips_dsp[] = { |
| 814 // no dither | 925 // no dither |
| 815 NULL, | 926 NULL, |
| 816 S32_D565_Blend_mips_dsp, | 927 S32_D565_Blend_mips_dsp, |
| 817 S32A_D565_Opaque_mips_dsp, | 928 S32A_D565_Opaque_mips_dsp, |
| 818 S32A_D565_Blend_mips_dsp, | 929 S32A_D565_Blend_mips_dsp, |
| 819 | 930 |
| 820 // dither | 931 // dither |
| (...skipping 18 matching lines...) Expand all Loading... |
| 839 return platform_32_procs_mips_dsp[flags]; | 950 return platform_32_procs_mips_dsp[flags]; |
| 840 } | 951 } |
| 841 | 952 |
| 842 SkBlitRow::ColorRectProc PlatformColorRectProcFactory() { | 953 SkBlitRow::ColorRectProc PlatformColorRectProcFactory() { |
| 843 return NULL; | 954 return NULL; |
| 844 } | 955 } |
| 845 | 956 |
| 846 SkBlitRow::ColorProc SkBlitRow::PlatformColorProc() { | 957 SkBlitRow::ColorProc SkBlitRow::PlatformColorProc() { |
| 847 return NULL; | 958 return NULL; |
| 848 } | 959 } |
| OLD | NEW |