| OLD | NEW |
|---|
| 1 /* | 1 /* |
| 2 * Written by J.T. Conklin <jtc@netbsd.org>. | 2 * Written by J.T. Conklin <jtc@netbsd.org>. |
| 3 * Public domain. | 3 * Public domain. |
| 4 */ | 4 */ |
| 5 | 5 |
| 6 #include <machine/asm.h> | 6 #include <machine/asm.h> |
| 7 | 7 |
| 8 RCSID("$NetBSD: s_ceilf.S,v 1.3 1995/05/08 23:52:44 jtc Exp $") | 8 RCSID("$NetBSD: s_ceilf.S,v 1.3 1995/05/08 23:52:44 jtc Exp $") |
| 9 | 9 |
| 10 ENTRY(__ceilf) | 10 ENTRY(__ceilf) |
| 11 flds 4(%esp) | 11 flds 4(%esp) |
| 12 subl $8,%esp | 12 subl $8,%esp |
| 13 | 13 |
| 14 fstcw 4(%esp) /* store fpu control word */ | 14 fstcw 4(%esp) /* store fpu control word */ |
| 15 | 15 |
| 16 /* We use here %edx although only the low 1 bits are defined. | 16 /* We use here %edx although only the low 1 bits are defined. |
| 17 But none of the operations should care and they are faster | 17 But none of the operations should care and they are faster |
| 18 than the 16 bit operations. */ | 18 than the 16 bit operations. */ |
| 19 movl $0x0800,%edx /* round towards +oo */ | 19 movl $0x0800,%edx /* round towards +oo */ |
| 20 orl 4(%esp),%edx | 20 orl 4(%esp),%edx |
| 21 andl $0xfbff,%edx | 21 andl $0xfbff,%edx |
| 22 movl %edx,(%esp) | 22 movl %edx,(%esp) |
| 23 fldcw (%esp) /* load modified control word */ | 23 fldcw (%esp) /* load modified control word */ |
| 24 | 24 |
| 25 frndint /* round */ | 25 frndint /* round */ |
| 26 | 26 |
| 27 fldcw 4(%esp) /* restore original control word */ | 27 fldcw 4(%esp) /* restore original control word */ |
| 28 | 28 |
| 29 addl $8,%esp | 29 addl $8,%esp |
| 30 » ret | 30 » NACLRET |
| 31 END (__ceilf) | 31 END (__ceilf) |
| 32 weak_alias (__ceilf, ceilf) | 32 weak_alias (__ceilf, ceilf) |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 3539003:
Fix up RET instructions in sysdeps/i386/fpu (Closed)
Base URL: ssh://gitrw.chromium.org/nacl-glibc