Add support for vector types and vector constants.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 67 matching lines @@
 #undef X
   };
 const size_t TableIcmp64Size = llvm::array_lengthof(TableIcmp64);
 
 InstX8632Br::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
   size_t Index = static_cast<size_t>(Cond);
   assert(Index < TableIcmp32Size);
   return TableIcmp32[Index].Mapping;
 }
 
+// Output a valid assembly identifier for the specified type. This is
+// needed for representing vector types because the default Ostream
+// operator<< implementation does not output a valid assembly identifier
+// when the argument is a vector type.
+void emitAsmLabelForType(Ostream &OS, Type Ty) {
+  if (isVectorType(Ty)) {
+    OS << "v" << typeNumElements(Ty);
+  }
+  OS << typeElementType(Ty);
+}
+
 // In some cases, there are x-macros tables for both high-level and
 // low-level instructions/operands that use the same enum key value.
 // The tables are kept separate to maintain a proper separation
 // between abstraction layers.  There is a risk that the tables
 // could get out of sync if enum values are reordered or if entries
 // are added or deleted.  This dummy function uses static_assert to
 // ensure everything is kept in sync.
 void xMacroIntegrityCheck() {
   // Validate the enum values in FCMPX8632_TABLE.
   {
@@ skipping 55 matching lines @@
   {
     // Define a temporary set of enum values based on low-level
     // table entries.
     enum _tmp_enum {
 #define X(tag, cvt, sdss, width) _tmp_##tag,
       ICETYPEX8632_TABLE
 #undef X
           _num
     };
 // Define a set of constants based on high-level table entries.
-#define X(tag, size, align, str) static const int _table1_##tag = tag;
+#define X(tag, size, align, elts, elty, str)                                   \
+  static const int _table1_##tag = tag;
     ICETYPE_TABLE;
 #undef X
 // Define a set of constants based on low-level table entries,
 // and ensure the table entry keys are consistent.
 #define X(tag, cvt, sdss, width)                                               \
   static const int _table2_##tag = _tmp_##tag;                                 \
   STATIC_ASSERT(_table1_##tag == _table2_##tag);
     ICETYPEX8632_TABLE;
 #undef X
 // Repeat the static asserts with respect to the high-level
 // table entries in case the high-level table has extra entries.
-#define X(tag, size, align, str) STATIC_ASSERT(_table1_##tag == _table2_##tag);
+#define X(tag, size, align, elts, elty, str)                                   \
+  STATIC_ASSERT(_table1_##tag == _table2_##tag);
     ICETYPE_TABLE;
 #undef X
   }
 }
 
 } // end of anonymous namespace
 
 TargetX8632::TargetX8632(Cfg *Func)
     : TargetLowering(Func), IsEbpBasedFrame(false), FrameSizeLocals(0),
       LocalsSizeBytes(0), NextLabelNumber(0), ComputedLiveRanges(false),
@@ skipping 488 matching lines @@
   typedef ConstantDouble IceType;
   static const Type Ty = IceType_f64;
   static const char *TypeName;
   static const char *AsmTag;
   static const char *PrintfString;
 };
 const char *PoolTypeConverter<double>::TypeName = "double";
 const char *PoolTypeConverter<double>::AsmTag = ".quad";
 const char *PoolTypeConverter<double>::PrintfString = "0x%llx";
 
-template <typename T> void TargetX8632::emitConstantPool() const {
+template <typename T> void TargetX8632::emitScalarConstantPool() const {
   Ostream &Str = Ctx->getStrEmit();
   Type Ty = T::Ty;
   SizeT Align = typeAlignInBytes(Ty);
   ConstantList Pool = Ctx->getConstantPool(Ty);
 
   Str << "\t.section\t.rodata.cst" << Align << ",\"aM\",@progbits," << Align
       << "\n";
   Str << "\t.align\t" << Align << "\n";
   for (ConstantList::const_iterator I = Pool.begin(), E = Pool.end(); I != E;
        ++I) {
     typename T::IceType *Const = llvm::cast<typename T::IceType>(*I);
     typename T::PrimitiveFpType Value = Const->getValue();
     // Use memcpy() to copy bits from Value into RawValue in a way
     // that avoids breaking strict-aliasing rules.
     typename T::PrimitiveIntType RawValue;
     memcpy(&RawValue, &Value, sizeof(Value));
     char buf[30];
     int CharsPrinted =
         snprintf(buf, llvm::array_lengthof(buf), T::PrintfString, RawValue);
     assert(CharsPrinted >= 0 &&
            (size_t)CharsPrinted < llvm::array_lengthof(buf));
     (void)CharsPrinted; // avoid warnings if asserts are disabled
     Str << "L$" << Ty << "$" << Const->getPoolEntryID() << ":\n";
     Str << "\t" << T::AsmTag << "\t" << buf << "\t# " << T::TypeName << " "
         << Value << "\n";
   }
 }
 
+void TargetX8632::emitVectorConstantPool() const {
+  Ostream &Str = Ctx->getStrEmit();
+
+  // Although the PNaCl ABI doesn't require it, all vector constants are
+  // aligned to 16 bytes to allow for aligned loads.
+  const unsigned Align = VECT128_BYTES;
+
+  Str << "\t.section\t.rodata.cst" << Align << ",\"aM\",@progbits," << Align
+      << "\n";
+  Str << "\t.align\t" << Align << "\n";
+
+  // Emit each (128 bit) vector.
+  // Non-I1 vectors are all in the same constant pool.
+  ConstantList Vectors = Ctx->getConstantPool(IceType_v8i16);
+  for (ConstantList::const_iterator I = Vectors.begin(), E = Vectors.end();
+       I != E; ++I) {
+    ConstantVector *Vector = llvm::cast<ConstantVector>(*I);
+    Vect128 Value = Vector->getValue();
+    assert(Value.size() == VECT128_BYTES);
+    const char *Data = Value.data();
+    Str << "L$";
+    emitAsmLabelForType(Str, Vector->getType());
+    Str << "$" << Vector->getPoolEntryID() << ":\n";
+    for (unsigned Element = 0; Element < 4; ++Element) {
+      uint32_t RawValue;
+      memcpy(&RawValue, &Data[4 * Element], 4);
+      char buf[30];
+      int CharsPrinted =
+          snprintf(buf, llvm::array_lengthof(buf), "0x%x", RawValue);
+      assert(CharsPrinted >= 0 &&
+             (size_t)CharsPrinted < llvm::array_lengthof(buf));
+      Str << "\t"
+          << ".long"
+          << "\t" << buf << "\t"
+          << "\n";
+    }
+  }
+
+  // Emit each I1 vector expanded to a 128 bit constant.
+  // All I1 vectors are in the same constant pool.
+  ConstantList BitVectors = Ctx->getConstantPool(IceType_v4i1);
+  for (ConstantList::const_iterator I = BitVectors.begin(),
+                                    E = BitVectors.end();
+       I != E; ++I) {
+    ConstantBitVector *BitVector = llvm::cast<ConstantBitVector>(*I);
+    BitVect Value = BitVector->getValue();
+    Str << "L$";
+    emitAsmLabelForType(Str, BitVector->getType());
+    Str << "$" << BitVector->getPoolEntryID() << ":\n";
+    const char *AsmString = NULL;
+    switch (BitVector->getType()) {
+    default:
+      llvm_unreachable("Unknown type");
+    case IceType_v4i1:
+      AsmString = ".long";
+      break;
+    case IceType_v8i1:
+      AsmString = ".short";
+      break;
+    case IceType_v16i1:
+      AsmString = ".byte";
+      break;
+    }
+    unsigned NumElements = Value.size();
+    for (unsigned Element = 0; Element < NumElements; ++Element) {
+      Str << "\t" << AsmString << "\t"
+          << "0x";
+      Str << (Value[Element] ? "1" : "0");
+      Str << "\t"
+          << "\n";
+    }
+  }
+}
+
 void TargetX8632::emitConstants() const {
-  emitConstantPool<PoolTypeConverter<float> >();
-  emitConstantPool<PoolTypeConverter<double> >();
+  emitScalarConstantPool<PoolTypeConverter<float> >();
+  emitScalarConstantPool<PoolTypeConverter<double> >();
+  emitVectorConstantPool();
 
   // No need to emit constants from the int pool since (for x86) they
   // are embedded as immediates in the instructions.
 }
 
 void TargetX8632::split64(Variable *Var) {
   switch (Var->getType()) {
   default:
     return;
   case IceType_i64:
@@ skipping 564 matching lines @@
     }
     StackOffset += typeWidthInBytesOnStack(Arg->getType());
   }
   // Generate the call instruction.  Assign its result to a temporary
   // with high register allocation weight.
   Variable *Dest = Instr->getDest();
   Variable *eax = NULL; // doubles as RegLo as necessary
   Variable *edx = NULL;
   if (Dest) {
     switch (Dest->getType()) {
+    case IceType_v4i1:
+    case IceType_v8i1:
+    case IceType_v16i1:
+    case IceType_v16i8:
+    case IceType_v8i16:
+    case IceType_v4i32:
+    case IceType_v4f32:
     case IceType_NUM:
       llvm_unreachable("Invalid Call dest type");
       break;
     case IceType_void:
       break;
     case IceType_i1:
     case IceType_i8:
     case IceType_i16:
     case IceType_i32:
       eax = makeReg(Dest->getType(), Reg_eax);
@@ skipping 954 matching lines @@
   if (Inst->hasRetValue()) {
     Operand *Src0 = legalize(Inst->getRetValue());
     if (Src0->getType() == IceType_i64) {
       Variable *eax = legalizeToVar(loOperand(Src0), false, Reg_eax);
       Variable *edx = legalizeToVar(hiOperand(Src0), false, Reg_edx);
       Reg = eax;
       Context.insert(InstFakeUse::create(Func, edx));
     } else if (Src0->getType() == IceType_f32 ||
                Src0->getType() == IceType_f64) {
       _fld(Src0);
+    } else if (isVectorType(Src0->getType())) {
+      Reg = legalizeToVar(Src0, false, Reg_xmm0);
     } else {
       _mov(Reg, Src0, Reg_eax);
     }
   }
   _ret(Reg);
   // Add a fake use of esp to make sure esp stays alive for the entire
   // function.  Otherwise post-call esp adjustments get dead-code
   // eliminated.  TODO: Are there more places where the fake use
   // should be inserted?  E.g. "void f(int n){while(1) g(n);}" may not
   // have a ret instruction.
@@ skipping 101 matching lines @@
   _br(Inst->getLabelDefault());
 }
 
 void TargetX8632::lowerUnreachable(const InstUnreachable * /*Inst*/) {
   const SizeT MaxSrcs = 0;
   Variable *Dest = NULL;
   InstCall *Call = makeHelperCall("ice_unreachable", Dest, MaxSrcs);
   lowerCall(Call);
 }
 
+// Helper for legalize() to emit the right code to lower an operand to a
+// register of the appropriate type.
+Variable *TargetX8632::copyToReg(Operand *Src, int32_t RegNum) {
+  Type Ty = Src->getType();
+  Variable *Reg = makeReg(Ty, RegNum);
+  if (isVectorType(Src->getType())) {
+    _movp(Reg, Src);
+  } else {
+    _mov(Reg, Src);
+  }
+  return Reg;
+}
+
 Operand *TargetX8632::legalize(Operand *From, LegalMask Allowed,
                                bool AllowOverlap, int32_t RegNum) {
   // Assert that a physical register is allowed.  To date, all calls
   // to legalize() allow a physical register.  If a physical register
   // needs to be explicitly disallowed, then new code will need to be
   // written to force a spill.
   assert(Allowed & Legal_Reg);
   // If we're asking for a specific physical register, make sure we're
   // not allowing any other operand kinds.  (This could be future
   // work, e.g. allow the shl shift amount to be either an immediate
@@ skipping 12 matching lines @@
     if (Index) {
       RegIndex = legalizeToVar(Index, true);
     }
     if (Base != RegBase || Index != RegIndex) {
       From = OperandX8632Mem::create(
           Func, Mem->getType(), RegBase, Mem->getOffset(), RegIndex,
           Mem->getShift(), Mem->getSegmentRegister());
     }
 
     if (!(Allowed & Legal_Mem)) {
-      Variable *Reg = makeReg(From->getType(), RegNum);
-      _mov(Reg, From, RegNum);
-      From = Reg;
+      From = copyToReg(From, RegNum);
     }
     return From;
   }
   if (llvm::isa<Constant>(From)) {
     if (llvm::isa<ConstantUndef>(From)) {
       // Lower undefs to zero.  Another option is to lower undefs to an
       // uninitialized register; however, using an uninitialized register
       // results in less predictable code.
       //
       // If in the future the implementation is changed to lower undef
       // values to uninitialized registers, a FakeDef will be needed:
       //     Context.insert(InstFakeDef::create(Func, Reg));
       // This is in order to ensure that the live range of Reg is not
       // overestimated.  If the constant being lowered is a 64 bit value,
       // then the result should be split and the lo and hi components will
       // need to go in uninitialized registers.
       From = Ctx->getConstantZero(From->getType());
     }
     bool NeedsReg =
         !(Allowed & Legal_Imm) ||
-        // ConstantFloat and ConstantDouble are actually memory operands.
+        // ConstantFloat, ConstantDouble, and vector constants are
+        // actually memory operands.
         (!(Allowed & Legal_Mem) &&
-         (From->getType() == IceType_f32 || From->getType() == IceType_f64));
+         (From->getType() == IceType_f32 || From->getType() == IceType_f64 ||
+          isVectorType(From->getType())));
     if (NeedsReg) {
-      Variable *Reg = makeReg(From->getType(), RegNum);
-      _mov(Reg, From);
-      From = Reg;
+      From = copyToReg(From, RegNum);
     }
     return From;
   }
   if (Variable *Var = llvm::dyn_cast<Variable>(From)) {
     // We need a new physical register for the operand if:
     //   Mem is not allowed and Var->getRegNum() is unknown, or
     //   RegNum is required and Var->getRegNum() doesn't match.
     if ((!(Allowed & Legal_Mem) && !Var->hasReg()) ||
         (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
-      Variable *Reg = makeReg(From->getType(), RegNum);
+      Variable *Reg = copyToReg(From, RegNum);
       if (RegNum == Variable::NoRegister) {
         Reg->setPreferredRegister(Var, AllowOverlap);
       }
-      _mov(Reg, From);
       From = Reg;
     }
     return From;
   }
   llvm_unreachable("Unhandled operand kind in legalize()");
   return From;
 }
 
 // Provide a trivial wrapper to legalize() for this common usage.
 Variable *TargetX8632::legalizeToVar(Operand *From, bool AllowOverlap,
@@ skipping 81 matching lines @@
         }
         assert(AvailableTypedRegisters.any());
         int32_t RegNum = AvailableTypedRegisters.find_first();
         Var->setRegNum(RegNum);
         AvailableRegisters[RegNum] = false;
       }
     }
   }
 }
 
+template <> void ConstantInteger::emit(GlobalContext *Ctx) const {
+  Ostream &Str = Ctx->getStrEmit();
+  Str << getValue();
+}
+
 template <> void ConstantFloat::emit(GlobalContext *Ctx) const {
   Ostream &Str = Ctx->getStrEmit();
   // It would be better to prefix with ".L$" instead of "L$", but
   // llvm-mc doesn't parse "dword ptr [.L$foo]".
   Str << "dword ptr [L$" << IceType_f32 << "$" << getPoolEntryID() << "]";
 }
 
 template <> void ConstantDouble::emit(GlobalContext *Ctx) const {
   Ostream &Str = Ctx->getStrEmit();
   Str << "qword ptr [L$" << IceType_f64 << "$" << getPoolEntryID() << "]";
 }
 
+template <> void ConstantVector::emit(GlobalContext *Ctx) const {
+  Ostream &Str = Ctx->getStrEmit();
+  Str << "xmmword ptr [L$";
+  emitAsmLabelForType(Str, getType());
+  Str << "$" << getPoolEntryID() << "]";
+}
+
+template <> void ConstantBitVector::emit(GlobalContext *Ctx) const {
+  Ostream &Str = Ctx->getStrEmit();
+  Str << "xmmword ptr [L$";
+  emitAsmLabelForType(Str, getType());
+  Str << "$" << getPoolEntryID() << "]";
+}
+
 } // end of namespace Ice