Chromium Code Reviews| Index: src/base/atomicops_internals_x86_gcc.cc |
| diff --git a/src/base/atomicops_internals_x86_gcc.cc b/src/base/atomicops_internals_x86_gcc.cc |
| index ffc8bce0b0ac6b22053ecb04eff6143250d70e5e..f2cddbe9f9e6aaa69d91ac3410e2c1e722db7e18 100644 |
| --- a/src/base/atomicops_internals_x86_gcc.cc |
| +++ b/src/base/atomicops_internals_x86_gcc.cc |
| @@ -42,6 +42,7 @@ namespace base { |
| // default values should hopefully be pretty safe. |
| struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { |
| false, // bug can't exist before process spawns multiple threads |
| + false, // no SSE2 |
|
Jakob Kummerow
2014/06/23 12:21:18
Missing #ifdef. I was wondering how this would com
|
| }; |
| } } // namespace v8::base |
| @@ -87,6 +88,11 @@ void AtomicOps_Internalx86CPUFeaturesInit() { |
| } else { |
| AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false; |
| } |
| + |
| +#if !defined(__SSE2__) |
| + // edx bit 26 is SSE2 which we use to tell use whether we can use mfence |
| + AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1); |
| +#endif |
| } |
| class AtomicOpsx86Initializer { |