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Side by Side Diff: src/IceTargetLoweringX8632.cpp

Issue 341683002: Add ss/sd suffix to InstX8632Store and legalize FP constants. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: another label Created 6 years, 6 months ago
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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the TargetLoweringX8632 class, which 10 // This file implements the TargetLoweringX8632 class, which
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2167 // 2167 //
2168 // If in the future the implementation is changed to lower undef 2168 // If in the future the implementation is changed to lower undef
2169 // values to uninitialized registers, a FakeDef will be needed: 2169 // values to uninitialized registers, a FakeDef will be needed:
2170 // Context.insert(InstFakeDef::create(Func, Reg)); 2170 // Context.insert(InstFakeDef::create(Func, Reg));
2171 // This is in order to ensure that the live range of Reg is not 2171 // This is in order to ensure that the live range of Reg is not
2172 // overestimated. If the constant being lowered is a 64 bit value, 2172 // overestimated. If the constant being lowered is a 64 bit value,
2173 // then the result should be split and the lo and hi components will 2173 // then the result should be split and the lo and hi components will
2174 // need to go in uninitialized registers. 2174 // need to go in uninitialized registers.
2175 From = Ctx->getConstantZero(From->getType()); 2175 From = Ctx->getConstantZero(From->getType());
2176 } 2176 }
2177 if (!(Allowed & Legal_Imm)) { 2177 bool NeedsReg = !(Allowed & Legal_Imm) ||
2178 // ConstantFloat and ConstantDouble are actually memory operands.
2179 (!(Allowed & Legal_Mem) && (From->getType() == IceType_f32 ||
2180 From->getType() == IceType_f64));
2181 if (NeedsReg) {
2178 Variable *Reg = makeReg(From->getType(), RegNum); 2182 Variable *Reg = makeReg(From->getType(), RegNum);
2179 _mov(Reg, From); 2183 _mov(Reg, From);
2180 From = Reg; 2184 From = Reg;
2181 } 2185 }
2182 return From; 2186 return From;
2183 } 2187 }
2184 if (Variable *Var = llvm::dyn_cast<Variable>(From)) { 2188 if (Variable *Var = llvm::dyn_cast<Variable>(From)) {
2185 // We need a new physical register for the operand if: 2189 // We need a new physical register for the operand if:
2186 // Mem is not allowed and Var->getRegNum() is unknown, or 2190 // Mem is not allowed and Var->getRegNum() is unknown, or
2187 // RegNum is required and Var->getRegNum() doesn't match. 2191 // RegNum is required and Var->getRegNum() doesn't match.
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2283 // llvm-mc doesn't parse "dword ptr [.L$foo]". 2287 // llvm-mc doesn't parse "dword ptr [.L$foo]".
2284 Str << "dword ptr [L$" << IceType_f32 << "$" << getPoolEntryID() << "]"; 2288 Str << "dword ptr [L$" << IceType_f32 << "$" << getPoolEntryID() << "]";
2285 } 2289 }
2286 2290
2287 template <> void ConstantDouble::emit(GlobalContext *Ctx) const { 2291 template <> void ConstantDouble::emit(GlobalContext *Ctx) const {
2288 Ostream &Str = Ctx->getStrEmit(); 2292 Ostream &Str = Ctx->getStrEmit();
2289 Str << "qword ptr [L$" << IceType_f64 << "$" << getPoolEntryID() << "]"; 2293 Str << "qword ptr [L$" << IceType_f64 << "$" << getPoolEntryID() << "]";
2290 } 2294 }
2291 2295
2292 } // end of namespace Ice 2296 } // end of namespace Ice
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