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Side by Side Diff: src/IceTargetLoweringX8632.cpp

Issue 339783002: Add support for undef values in ICE IR. (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Comment about uninitialized registers Created 6 years, 6 months ago
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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the TargetLoweringX8632 class, which 10 // This file implements the TargetLoweringX8632 class, which
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2153 } 2153 }
2154 2154
2155 if (!(Allowed & Legal_Mem)) { 2155 if (!(Allowed & Legal_Mem)) {
2156 Variable *Reg = makeReg(From->getType(), RegNum); 2156 Variable *Reg = makeReg(From->getType(), RegNum);
2157 _mov(Reg, From, RegNum); 2157 _mov(Reg, From, RegNum);
2158 From = Reg; 2158 From = Reg;
2159 } 2159 }
2160 return From; 2160 return From;
2161 } 2161 }
2162 if (llvm::isa<Constant>(From)) { 2162 if (llvm::isa<Constant>(From)) {
2163 if (llvm::isa<ConstantUndef>(From)) {
2164 // Lower undefs to zero. Another option is to lower undefs to an
2165 // uninitialized register; however, using an uninitialized register
2166 // results in less predictable code.
2167 //
2168 // If in the future the implementation is changed to lower undef
2169 // values to uninitialized registers, a FakeDef will be needed:
2170 // Context.insert(InstFakeDef::create(Func, Reg));
2171 // This is in order to ensure that the live range of Reg is not
2172 // overestimated. If the constant being lowered is a 64 bit value,
2173 // then the result should be split and the lo and hi components will
2174 // need to go in uninitialized registers.
2175 From = Ctx->getConstantZero(From->getType());
2176 }
2163 if (!(Allowed & Legal_Imm)) { 2177 if (!(Allowed & Legal_Imm)) {
2164 Variable *Reg = makeReg(From->getType(), RegNum); 2178 Variable *Reg = makeReg(From->getType(), RegNum);
2165 _mov(Reg, From); 2179 _mov(Reg, From);
2166 From = Reg; 2180 From = Reg;
2167 } 2181 }
2168 return From; 2182 return From;
2169 } 2183 }
2170 if (Variable *Var = llvm::dyn_cast<Variable>(From)) { 2184 if (Variable *Var = llvm::dyn_cast<Variable>(From)) {
2171 // We need a new physical register for the operand if: 2185 // We need a new physical register for the operand if:
2172 // Mem is not allowed and Var->getRegNum() is unknown, or 2186 // Mem is not allowed and Var->getRegNum() is unknown, or
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2269 // llvm-mc doesn't parse "dword ptr [.L$foo]". 2283 // llvm-mc doesn't parse "dword ptr [.L$foo]".
2270 Str << "dword ptr [L$" << IceType_f32 << "$" << getPoolEntryID() << "]"; 2284 Str << "dword ptr [L$" << IceType_f32 << "$" << getPoolEntryID() << "]";
2271 } 2285 }
2272 2286
2273 template <> void ConstantDouble::emit(GlobalContext *Ctx) const { 2287 template <> void ConstantDouble::emit(GlobalContext *Ctx) const {
2274 Ostream &Str = Ctx->getStrEmit(); 2288 Ostream &Str = Ctx->getStrEmit();
2275 Str << "qword ptr [L$" << IceType_f64 << "$" << getPoolEntryID() << "]"; 2289 Str << "qword ptr [L$" << IceType_f64 << "$" << getPoolEntryID() << "]";
2276 } 2290 }
2277 2291
2278 } // end of namespace Ice 2292 } // end of namespace Ice
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