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Side by Side Diff: src/IceTargetLoweringX8632.cpp

Issue 339783002: Add support for undef values in ICE IR. (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Created 6 years, 6 months ago
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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the TargetLoweringX8632 class, which 10 // This file implements the TargetLoweringX8632 class, which
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2145 } 2145 }
2146 2146
2147 if (!(Allowed & Legal_Mem)) { 2147 if (!(Allowed & Legal_Mem)) {
2148 Variable *Reg = makeReg(From->getType(), RegNum); 2148 Variable *Reg = makeReg(From->getType(), RegNum);
2149 _mov(Reg, From, RegNum); 2149 _mov(Reg, From, RegNum);
2150 From = Reg; 2150 From = Reg;
2151 } 2151 }
2152 return From; 2152 return From;
2153 } 2153 }
2154 if (llvm::isa<Constant>(From)) { 2154 if (llvm::isa<Constant>(From)) {
2155 if (!(Allowed & Legal_Imm)) { 2155 if (llvm::isa<ConstantUndef>(From)) {
2156 // Undef values are lowered to a register.
Jim Stichnoth 2014/06/17 06:28:07 Maybe change "lowered to a register" to "lowered t
wala 2014/06/17 20:38:02 I agree that the comment needs to be clarified tha
2157 Variable *Reg = makeReg(From->getType(), RegNum);
2158 // Insert a FakeDef so that the live range of Reg is not overestimated.
2159 Context.insert(InstFakeDef::create(Func, Reg));
2160 From = Reg;
2161 } else if (!(Allowed & Legal_Imm)) {
2156 Variable *Reg = makeReg(From->getType(), RegNum); 2162 Variable *Reg = makeReg(From->getType(), RegNum);
2157 _mov(Reg, From); 2163 _mov(Reg, From);
2158 From = Reg; 2164 From = Reg;
2159 } 2165 }
2160 return From; 2166 return From;
2161 } 2167 }
2162 if (Variable *Var = llvm::dyn_cast<Variable>(From)) { 2168 if (Variable *Var = llvm::dyn_cast<Variable>(From)) {
2163 // We need a new physical register for the operand if: 2169 // We need a new physical register for the operand if:
2164 // Mem is not allowed and Var->getRegNum() is unknown, or 2170 // Mem is not allowed and Var->getRegNum() is unknown, or
2165 // RegNum is required and Var->getRegNum() doesn't match. 2171 // RegNum is required and Var->getRegNum() doesn't match.
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2261 // llvm-mc doesn't parse "dword ptr [.L$foo]". 2267 // llvm-mc doesn't parse "dword ptr [.L$foo]".
2262 Str << "dword ptr [L$" << IceType_f32 << "$" << getPoolEntryID() << "]"; 2268 Str << "dword ptr [L$" << IceType_f32 << "$" << getPoolEntryID() << "]";
2263 } 2269 }
2264 2270
2265 template <> void ConstantDouble::emit(GlobalContext *Ctx) const { 2271 template <> void ConstantDouble::emit(GlobalContext *Ctx) const {
2266 Ostream &Str = Ctx->getStrEmit(); 2272 Ostream &Str = Ctx->getStrEmit();
2267 Str << "qword ptr [L$" << IceType_f64 << "$" << getPoolEntryID() << "]"; 2273 Str << "qword ptr [L$" << IceType_f64 << "$" << getPoolEntryID() << "]";
2268 } 2274 }
2269 2275
2270 } // end of namespace Ice 2276 } // end of namespace Ice
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