Remove the definition of AtomicOps_Internalx86CPUFeatures from base/atomicops_internals_tsan.h

base/atomicops_internals_tsan.h

 // Copyright (c) 2012 The Chromium Authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // This file is an internal atomic implementation for compiler-based
 // ThreadSanitizer. Use base/atomicops.h instead.
 
 #ifndef BASE_ATOMICOPS_INTERNALS_TSAN_H_
 #define BASE_ATOMICOPS_INTERNALS_TSAN_H_
 
-#include "base/base_export.h"
-
-// This struct is not part of the public API of this module; clients may not
-// use it.  (However, it's exported via BASE_EXPORT because clients implicitly
-// do use it at link time by inlining these functions.)
-// Features of this x86.  Values may not be correct before main() is run,
-// but are set conservatively.
-struct AtomicOps_x86CPUFeatureStruct {
-  bool has_amd_lock_mb_bug;  // Processor has AMD memory-barrier bug; do lfence
-                             // after acquire compare-and-swap.
-};
-BASE_EXPORT extern struct AtomicOps_x86CPUFeatureStruct
-    AtomicOps_Internalx86CPUFeatures;
-
-#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
-
 #include <sanitizer/tsan_interface_atomic.h>
 
 namespace base {
 namespace subtle {
 
 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
                                          Atomic32 old_value,
                                          Atomic32 new_value) {
   Atomic32 cmp = old_value;
   __tsan_atomic32_compare_exchange_strong(ptr, &cmp, new_value,
@@ skipping 155 matching lines @@
   return cmp;
 }
 
 inline void MemoryBarrier() {
   __tsan_atomic_thread_fence(__tsan_memory_order_seq_cst);
 }
 
 }  // namespace base::subtle
 }  // namespace base
 
-#undef ATOMICOPS_COMPILER_BARRIER
-
 #endif  // BASE_ATOMICOPS_INTERNALS_TSAN_H_