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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
6 | 6 |
7 #include "src/v8.h" | 7 #include "src/v8.h" |
8 | 8 |
9 #if V8_TARGET_ARCH_ARM | 9 #if V8_TARGET_ARCH_ARM |
10 | 10 |
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247 } | 247 } |
248 | 248 |
249 | 249 |
250 void MacroAssembler::Move(DwVfpRegister dst, DwVfpRegister src) { | 250 void MacroAssembler::Move(DwVfpRegister dst, DwVfpRegister src) { |
251 if (!dst.is(src)) { | 251 if (!dst.is(src)) { |
252 vmov(dst, src); | 252 vmov(dst, src); |
253 } | 253 } |
254 } | 254 } |
255 | 255 |
256 | 256 |
| 257 void MacroAssembler::Mls(Register dst, Register src1, Register src2, |
| 258 Register srcA, Condition cond) { |
| 259 if (CpuFeatures::IsSupported(MLS)) { |
| 260 CpuFeatureScope scope(this, MLS); |
| 261 mls(dst, src1, src2, srcA, cond); |
| 262 } else { |
| 263 ASSERT(!dst.is(srcA)); |
| 264 mul(ip, src1, src2, LeaveCC, cond); |
| 265 sub(dst, srcA, ip, LeaveCC, cond); |
| 266 } |
| 267 } |
| 268 |
| 269 |
257 void MacroAssembler::And(Register dst, Register src1, const Operand& src2, | 270 void MacroAssembler::And(Register dst, Register src1, const Operand& src2, |
258 Condition cond) { | 271 Condition cond) { |
259 if (!src2.is_reg() && | 272 if (!src2.is_reg() && |
260 !src2.must_output_reloc_info(this) && | 273 !src2.must_output_reloc_info(this) && |
261 src2.immediate() == 0) { | 274 src2.immediate() == 0) { |
262 mov(dst, Operand::Zero(), LeaveCC, cond); | 275 mov(dst, Operand::Zero(), LeaveCC, cond); |
263 } else if (!src2.is_single_instruction(this) && | 276 } else if (!src2.is_single_instruction(this) && |
264 !src2.must_output_reloc_info(this) && | 277 !src2.must_output_reloc_info(this) && |
265 CpuFeatures::IsSupported(ARMv7) && | 278 CpuFeatures::IsSupported(ARMv7) && |
266 IsPowerOf2(src2.immediate() + 1)) { | 279 IsPowerOf2(src2.immediate() + 1)) { |
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4075 sub(result, result, Operand(dividend)); | 4088 sub(result, result, Operand(dividend)); |
4076 } | 4089 } |
4077 if (ms.shift() > 0) mov(result, Operand(result, ASR, ms.shift())); | 4090 if (ms.shift() > 0) mov(result, Operand(result, ASR, ms.shift())); |
4078 add(result, result, Operand(dividend, LSR, 31)); | 4091 add(result, result, Operand(dividend, LSR, 31)); |
4079 } | 4092 } |
4080 | 4093 |
4081 | 4094 |
4082 } } // namespace v8::internal | 4095 } } // namespace v8::internal |
4083 | 4096 |
4084 #endif // V8_TARGET_ARCH_ARM | 4097 #endif // V8_TARGET_ARCH_ARM |
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