[ARM] tegra: add nvos/nvrm/nvmap drivers

arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_priv_ap_general.h

Index: arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_priv_ap_general.h
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_priv_ap_general.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_priv_ap_general.h
new file mode 100644
index 0000000000000000000000000000000000000000..ded480bdb41dda66d6fa353f262b41b16ff87755
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_priv_ap_general.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+ /** @file
+  *
+  * @b Description: Contains the maximum instance of the controller on soc.
+  * Must be >= the max of all chips.
+  */
+
+#ifndef INCLUDED_NVRM_PRIV_AP_GENERAL_H
+#define INCLUDED_NVRM_PRIV_AP_GENERAL_H
+
+
+// Dma specific definitions for latest SOC
+
+// Maximum number of DMA channels available on SOC.
+#define MAX_APB_DMA_CHANNELS        32
+
+
+// SPI specific definitions for latest SOC
+#define MAX_SPI_CONTROLLERS         8
+
+#define MAX_SLINK_CONTROLLERS       8
+
+
+// I2C specific definitions for latest soc
+#define MAX_I2C_CONTROLLERS         3
+
+#define MAX_DVC_CONTROLLERS         1
+
+#endif // INCLUDED_NVRM_PRIV_AP_GENERAL_H