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Side by Side Diff: arch/arm/mach-tegra/nv/include/nvos_linux_ioctls.h

Issue 3256004: [ARM] tegra: add nvos/nvrm/nvmap drivers (Closed) Base URL: ssh://git@gitrw.chromium.org/kernel.git
Patch Set: remove ap15 headers Created 10 years, 3 months ago
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1 /*
2 * Copyright (c) 2009 NVIDIA Corporation.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * Neither the name of the NVIDIA Corporation nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 */
32
33 #include <linux/ioctl.h>
34 #include "nvos.h"
35 #include "nvcommon.h"
36
37 #ifndef NVOS_LINUX_IOCTLS_H
38 #define NVOS_LINUX_IOCTLS_H
39
40 typedef struct
41 {
42 NvU32 IoctlCode;
43 NvU32 InBufferSize;
44 NvU32 InOutBufferSize;
45 NvU32 OutBufferSize;
46 void *pBuffer;
47 } NV_ALIGN(4) NvOsIoctlParams;
48
49 typedef struct
50 {
51 NvOsSemaphoreHandle sem;
52 NvU32 value;
53 NvError error;
54 } NV_ALIGN(4) NvOsSemaphoreIoctlParams;
55
56 typedef struct
57 {
58 NvOsSemaphoreHandle hOrig;
59 NvOsSemaphoreHandle hNew;
60 NvError Error;
61 } NV_ALIGN(4) NvOsSemaphoreUnmarshalParams;
62
63 typedef struct
64 {
65 NvOsSemaphoreHandle hOrig;
66 NvOsSemaphoreHandle hNew;
67 NvError Error;
68 } NV_ALIGN(4) NvOsSemaphoreCloneParams;
69
70 typedef struct
71 {
72 NvU32 nIrqs;
73 const NvU32 *Irqs;
74 NvOsSemaphoreHandle *SemaphoreList;
75 NvError errCode;
76 NvUPtr kernelHandle;
77 } NV_ALIGN(4) NvOsInterruptRegisterParams;
78
79 typedef struct
80 {
81 NvUPtr handle;
82 NvU32 arg;
83 NvError errCode;
84 } NV_ALIGN(4) NvOsInterruptOpParams;
85
86 typedef struct
87 {
88 NvUPtr handle;
89 NvU32 mask;
90 } NV_ALIGN(4) NvOsInterruptMaskParams;
91
92 typedef struct
93 {
94 NvU32 size;
95 char *text;
96 } NV_ALIGN(4) NvOsDebugStringParams;
97
98 typedef struct
99 {
100 NvOsPhysAddr base;
101 NvU32 size;
102 } NV_ALIGN(4) NvOsMemRangeParams;
103
104 #define NV_IOCTL_SEMAPHORE_CREATE _IOWR('N', 0x20, NvOsSemaphoreIoctlParams)
105 #define NV_IOCTL_SEMAPHORE_DESTROY _IOW('N', 0x21, NvOsSemaphoreHandle)
106 #define NV_IOCTL_SEMAPHORE_CLONE \
107 _IOWR('N', 0x22, NvOsSemaphoreCloneParams)
108 #define NV_IOCTL_SEMAPHORE_UNMARSHAL \
109 _IOWR('N', 0x23, NvOsSemaphoreUnmarshalParams)
110 #define NV_IOCTL_SEMAPHORE_SIGNAL _IOW('N', 0x24, NvOsSemaphoreHandle)
111 #define NV_IOCTL_SEMAPHORE_WAIT _IOW('N', 0x25, NvOsSemaphoreHandle)
112 #define NV_IOCTL_SEMAPHORE_WAIT_TIMEOUT \
113 _IOW('N', 0x26, NvOsSemaphoreIoctlParams)
114 #define NV_IOCTL_INTERRUPT_REGISTER \
115 _IOWR('N', 0x27, NvOsInterruptRegisterParams)
116 #define NV_IOCTL_INTERRUPT_UNREGISTER _IOWR('N', 0x28, NvOsInterruptOpParams)
117 #define NV_IOCTL_INTERRUPT_ENABLE _IOWR('N', 0x29, NvOsInterruptOpParams)
118 #define NV_IOCTL_INTERRUPT_DONE _IOWR('N', 0x2A, NvOsInterruptOpParams)
119 #define NV_IOCTL_INTERRUPT_MASK _IOWR('N', 0x2B, NvOsInterruptOpParams)
120 #define NV_IOCTL_GLOBAL_LOCK _IO('N', 0x2C)
121 #define NV_IOCTL_GLOBAL_UNLOCK _IO('N', 0x2D)
122 #define NV_IOCTL_DEBUG_STRING _IOW('N', 0x2E, NvOsDebugStringParams)
123 #define NV_IOCTL_MEMORY_RANGE _IOW('N', 0x2F, NvOsMemRangeParams)
124
125 #endif
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